Abstract: A semiconductor device comprising a substrate and an electronic circuit thereon is described. The electronic circuit comprises a first voltage provider node, a second voltage provider node, and an intermediary node connected to the first and second voltage provider node by a first and second network with a first and second resistance, respectively. The substrate is susceptible to conducting a substrate current. The semiconductor device further comprises a substrate current sensor. The first network is arranged to reduce the first resistance in response to the substrate current sensor signaling an increase of the substrate current and vice versa. Similarly, the second network is arranged to reduce the second resistance in response to the substrate current sensor signaling an increase of the substrate current and vice versa. A method of operating a semiconductor device is also disclosed.

Abstract: A semiconductor device comprises a plurality of output pads bondable to an output pin, a plurality of reference pads bondable to a reference pin, and output driver circuitry with a control terminal for receiving a control signal and arranged to drive the plurality of output pads relative to the plurality of reference pads in dependence on the control signal. The output driver circuitry includes driver sections and selection circuitry. Each driver section is arranged to drive an output pad relative to the single reference pad in dependence on a respective section control signal. The reference pads are connected in a one-to-one relationship to the driver sections. The output pads are connected in a one-to-one relationship to the driver sections. The selection circuitry provides the respective section control signals to the driver sections in dependence on at least one selection signal and the control signal.

Abstract: An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.

Abstract: An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.

Abstract: An oscillator circuit for providing an output clock signal is described. The oscillator circuit comprising a voltage reference, a first current source, first capacitor, first capacitor switch, second current source, second capacitor, second capacitor switch, first comparator, second comparator and flip-flop. The first comparator comprises a first chopper-stabilized comparator switchable between a compare phase and a zeroing phase in dependence on the output clock signal and arranged to operate in the compare phase in a first half-phase of the output clock signal to provide a first comparator output from comparing the first capacitor voltage to the reference voltage and in the zeroing phase in the second half-phase.

Abstract: A semiconductor device, comprising a substrate and an electronic circuit formed thereon is described. The substrate is susceptible to conducting a substrate current. The semiconductor device further comprises a substrate current sensor, which comprises a sensing line for sensing the potential at a charge collecting region; a supply node; and a current source connected between the supply node and the charge collecting region. The current source is arranged to inject a stationary current into the charge collecting region when the potential at the charge collecting region is below the supply potential. The sensing line comprises a monoflop, which is arranged to assume an unstable state when the potential at its input has exceeded a threshold and to return to a stable state when the potential at its input has remained below the threshold for at least a time period.

Abstract: A semiconductor device comprising a substrate and an electronic circuit thereon is described. The electronic circuit comprises a first voltage provider node, a second voltage provider node, and an intermediary node connected to the first and second voltage provider node by a first and second network with a first and second resistance, respectively. The substrate is susceptible to conducting a substrate current. The semiconductor device further comprises a substrate current sensor. The first network is arranged to reduce the first resistance in response to the substrate current sensor signaling an increase of the substrate current and vice versa. Similarly, the second network is arranged to reduce the second resistance in response to the substrate current sensor signaling an increase of the substrate current and vice versa. A method of operating a semiconductor device is also disclosed.

Abstract: A clock signal generation system is provided that includes a clock signal generating circuit arranged to provide a first clock signal having a selectable first clock rate; a divider circuit connected to receive the first clock signal and arranged to generate, depending on a division factor, a second clock signal from the first clock signal, having a constant second clock rate and being synchronized with the first clock signal; and a controller module connected to the divider circuit and arranged to change the division factor when a different first clock rate is selected, to keep the second clock rate constant and the second clock signal synchronized with the first clock signal.

Abstract: An oscillator circuit for providing an output clock signal is described. The oscillator circuit comprising a voltage reference, a first current source, first capacitor, first capacitor switch, second current source, second capacitor, second capacitor switch, first comparator, second comparator and flip-flop. The first comparator comprises a first chopper-stabilized comparator switchable between a compare phase and a zeroing phase in dependence on the output clock signal and arranged to operate in the compare phase in a first half-phase of the output clock signal to provide a first comparator output from comparing the first capacitor voltage to the reference voltage and in the zeroing phase in the second half-phase.

Abstract: A signalling circuit for a signal channel of a communication network comprises a communication network terminal connectable to the signal channel and to a voltage supply; an input terminal connectable to receive a transmit signal; a driver device comprising a first driver terminal connected to the communication network terminal, a second driver terminal connected to ground, and a driver control terminal connected to the input terminal; wherein the driver device is arranged to connect the communication network terminal to ground in response to a transition from a low to a high voltage driver control signal state of a driver control signal received at the driver control terminal.

Abstract: A semiconductor device comprises a plurality of output pads bondable to an output pin, a plurality of reference pads bondable to a reference pin, and output driver circuitry with a control terminal for receiving a control signal and arranged to drive the plurality of output pads relative to the plurality of reference pads in dependence on the control signal. The output driver circuitry includes driver sections and selection circuitry. Each driver section is arranged to drive an output pad relative to the single reference pad in dependence on a respective section control signal. The reference pads are connected in a one-to-one relationship to the driver sections. The output pads are connected in a one-to-one relationship to the driver sections. The selection circuitry provides the respective section control signals to the driver sections in dependence on at least one selection signal and the control signal.

Abstract: A semiconductor device comprises a substrate provided with a doping of a first type, on which an electronic circuit is provided surrounded by a circuit portion of the substrate provided with a doping of a second type; at least one pad for connecting the electronic circuit to an external device outside the substrate, surrounded by a pad portion provided with a doping of the second type; a sensing device comprising a sensor portion of the substrate provided with a doping of the first type, for sensing a parameter forming a measure for a local electrical potential of the substrate; and an evaluation unit connected to the sensing device, for providing an evaluation signal based on a difference between the parameter and a reference value.

Abstract: A signalling circuit for a signal channel of a communication network comprises a communication network terminal connectable to the signal channel and to a voltage supply; an input terminal connectable to receive a transmit signal; a driver device comprising a first driver terminal connected to the communication network terminal, a second driver terminal connected to ground, and a driver control terminal connected to the input terminal; wherein the driver device is arranged to connect the communication network terminal to ground in response to a transition from a low to a high voltage driver control signal state of a driver control signal received at the driver control terminal.

Abstract: A semiconductor device includes a substrate on which an electronic circuit is provided. One or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an amount of a current flowing between the substrate and at least one of the at least one pad. A control unit is connected to the current meter and the electronic circuit, for controlling the electronic circuit based on the measured parameter.

Abstract: A clock signal generation system is provided that includes a clock signal generating circuit arranged to provide a first clock signal having a selectable first clock rate; a divider circuit connected to receive the first clock signal and arranged to generate, depending on a division factor, a second clock signal from the first clock signal, having a constant second clock rate and being synchronized with the first clock signal; and a controller module connected to the divider circuit and arranged to change the division factor when a different first clock rate is selected, to keep the second clock rate constant and the second clock signal synchronized with the first clock signal.

Abstract: An electronic device comprises an application circuit; a first supply rail having a first electric potential; a second supply rail having a second electric potential different from the first electric potential; at least one terminal having a third electric potential, connected to the application circuit; and a protection circuit for protecting the application circuit from an injected current. The protection circuit comprises a first conductive line connected between the at least one terminal and the first supply rail, the first conductive line comprising a first switch having a first control input; and a first voltage amplifier circuit having a first input connected to the at least one terminal, a second input connected to the second supply rail and a first output connected to the first control input.

Abstract: A semiconductor device includes a substrate on which an electronic circuit is provided. Two or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an aggregate amount of a current flowing between the substrate and said pads. A control unit is connected to the current meter and the electronic circuit, for controlling the electronic circuit based on the measured parameter.

Abstract: An electronic device comprises an application circuit; a first supply rail having a first electric potential; a second supply rail having a second electric potential different from the first electric potential; at least one terminal having a third electric potential, connected to the application circuit; and a protection circuit for protecting the application circuit from an injected current. The protection circuit comprises a first conductive line connected between the at least one terminal and the first supply rail, the first conductive line comprising a first switch having a first control input; and a first voltage amplifier circuit having a first input connected to the at least one terminal, a second input connected to the second supply rail and a first output connected to the first control input.

Abstract: A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement.

Abstract: A semiconductor device comprises a substrate provided with a doping of a first type, on which an electronic circuit is provided surrounded by a circuit portion of the substrate provided with a doping of a second type; at least one pad for connecting the electronic circuit to an external device outside the substrate, surrounded by a pad portion provided with a doping of the second type; a sensing device comprising a sensor portion of the substrate provided with a doping of the first type, for sensing a parameter forming a measure for a local electrical potential of the substrate; and an evaluation unit connected to the sensing device, for providing an evaluation signal based on a difference between the parameter and a reference value.