Abstract: A predriver for a differential pair having a reduce voltage swing is disclosed having fast switching speed and low power consumption. The predriver includes a p-type MOS transistor, and a first and second n-type MOS transistor. The source of the p-type MOS couples to the first power supply rail. The gate of the first n-type MOS transistor couples to the gate of the p-type MOS transistor to form an input. The drain of the first n-type MOS transistor couples to the drain of the p-type MOS transistor to form an output. The drain of the second n-type MOS transistor couples to the source of the first n-type MOS transistor. The source of the second n-type MOS transistor couples to ground. The gate of the second n-type MOS transistor couples to the output. The presence of the second n-type MOS transistor alters the voltage swing of the predriver to be from the threshold voltage level to the full power supply voltage, substantially reducing the current or power consumption.

Abstract: An encoding scheme simplifies the TMDS encoding algorithm described in the DVI 1.0 specification while retaining compatibility with most existing DVI receivers. The generation of the Transition Control bit has been removed; and although the INV bit has a similar function to the DC bit in the DVI 1.0 standard, the algorithm for deriving it is very different. No attempt is made to maintain a DC balance on the cable. Instead, the INV bit is set to a ‘1’ for the purpose of removing ‘rogue’ character sequences; otherwise it is always set to a ‘0’.

Abstract: A predriver for a differential pair having a reduce voltage swing is disclosed having fast switching speed and low power consumption. The predriver includes a p-type MOS transistor, and a first and second n-type MOS transistor. The source of the p-type MOS couples to the first power supply rail. The gate of the first n-type MOS transistor couples to the gate of the p-type MOS transistor to form an input. The drain of the first n-type MOS transistor couples to the drain of the p-type MOS transistor to form an output. The drain of the second n-type MOS transistor couples to the source of the first n-type MOS transistor. The source of the second n-type MOS transistor couples to ground. The gate of the second n-type MOS transistor couples to the output. The presence of the second n-type MOS transistor alters the voltage swing of the predriver to be from the threshold voltage level to the full power supply voltage, substantially reducing the current or power consumption.

Abstract: A method of expanding data to a high-speed serial video link in such a way that it is invisible to existing receivers and such that auxiliary data, i.e. audio data, can be transmitted without any knowledge of the capabilities of the display to receive the auxiliary data.

Abstract: A method of adding auxiliary data, e.g., audio data, to a high-speed serial video link in such a way that it is invisible to existing receiver and such that auxiliary data, e.g., audio, can be transmitted without any knowledge of the capabilities of the display to receive the auxiliary data. Some of the DC balancing bits are used to transport the auxiliary data information over the link in a manner that does not change the data recovered by a DVI-CE receiver, or a legacy receiver (installed base). DC balancing is also maintained, but with differences over known techniques. Since the auxiliary data bits (which are occupying the time slots of the DC balance bits) will be interpreted by legacy receivers as DC balance bits, the data must be optionally inverted to remain consistent with the value of the auxiliary data bit being transmitted.

Abstract: An electronic system, such as a video decoder (80), includes a clock generator circuit (22, 22′) based upon a phase-locked loop (PLL) (25). The PLL (25) includes a voltage controlled oscillator (VCO) (30) that produces a plurality of evenly-spaced output phases, each of a locked frequency relative to a reference clock (CREF). A frequency synthesis circuit (27) receives a frequency selection value on control lines (FREQ) that include an integer and a fraction portion. The integer and fraction portion of the frequency selection value are added to the current contents of a register (40) that stores the previous integer value used to select the corresponding phase from VCO (30) for application to the clock input of a toggle flip-flop (36) from which the output clock (COUT) is generated. Use of the fraction portion permits a time-averaged clock frequency to be produced with more precision than the multiple phases output by the VCO (30).

Abstract: Apparatus for generating an output signal in response to the change in state of any one of a plurality of input signals. The apparatus includes decoding means for each possible combination of input signals, and by an appropriate arrangement of these decoding means, ensures that any change in input signal status causes an output signal to be generated by the arrangement of decoding means. The decoding means includes first and second arrays 10,12, each comprising a matrix of MOS FET's; the FET's 30.sub.ij of the first array 10 are p-channel devices and the FET's 32.sub.ij of the second array 12 are n-channel devices. The matrix of each array is a paralleled configuration of series-connected branches of FET's functioning as decoders. The branches of each array decode input signal combinations of minimum distance two from one another. Arrays 10 and 12 are interconnected in such a manner that they draw no dc current (other than device leakage current).

Abstract: A frequency doubler having adaptive biasing includes one shot circuits 10 and 12, which are responsive to particular transitions of an input signal for generating pulsed signals at each such transition. The widths of the pulses are determined by the magnitude of a bias current supplied to the one shot circuits. The pulsed signals of one shot circuits 10 and 12 are combined by OR gate 14 to provide an output signal whose frequency is twice the frequency of the input signal. A low-pass filter 16, coupled to the output signal, produces a signal which is a measure of the average voltage level of the output signal. Voltage-to-current converting FET 18, responsive to the average voltage level of the output signal, supplies bias current to one shots 10 and 12. Comparators 20 and 22 detect when the average voltage level is not within a predetermined range, and enable either up or down counting of digital counter 24.

Abstract: Flanged bearing bushes are described, the bearing bushes comprising a journal bearing element and a thrust flange bearing element on at least one end face of the journal bearing element, the at least one end face of said journal having at least two axially directed recesses adapted to receive generally axially directed tabs formed from thrust flange material and which tabs are fixed in position in the recesses by deformation of journal bearing element material adjacent the axially directed recesses. The flange element may be of generally annular, rectangular or any other polygonal shape.

Abstract: Flanged bearing bushes are described, the bush comprising a journal bearing element and a thrust flange bearing element on at least one end of the journal member, the journal bearing member having a reduced diameter portion and a shoulder formed on the outer diameter of the at least one end having the flange element wherein the flange element is received on the reduced diameter portion with the rear face of the flange supported by the shoulder on the journal bearing member end, and the flange member being retained on the journal bearing membered by deformation of material on the reduced diameter portion of the journal bearing member into recesses formed in the bore of the flange element.