Patents by Inventor Hugo Burke
Hugo Burke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11217577Abstract: A method includes providing a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, forming a switching device in an active region of the semiconductor substrate, the switching device having electrically conductive gate and field electrodes, forming an intermetal dielectric layer on the main surface over the active region and an inactive region that is laterally spaced apart from the active region, forming a source pad in the first metallization layer over the active region, forming a resistor trench in the inactive region, the resistor trench having a resistance section that is disposed below the main surface, and forming an electrical connection between the source pad and the field electrode that comprises the resistor. The resistor forms an exclusive current path between the source pad and the field electrode.Type: GrantFiled: February 13, 2020Date of Patent: January 4, 2022Assignee: Infineon Technologies Americas Corp.Inventors: Hugo Burke, Kapil Kelkar, Ling Ma
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Publication number: 20200185377Abstract: A method includes providing a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, forming a switching device in an active region of the semiconductor substrate, the switching device having electrically conductive gate and field electrodes, forming an intermetal dielectric layer on the main surface over the active region and an inactive region that is laterally spaced apart from the active region, forming a source pad in the first metallization layer over the active region, forming a resistor trench in the inactive region, the resistor trench having a resistance section that is disposed below the main surface, and forming an electrical connection between the source pad and the field electrode that comprises the resistor. The resistor forms an exclusive current path between the source pad and the field electrode.Type: ApplicationFiled: February 13, 2020Publication date: June 11, 2020Inventors: Hugo Burke, Kapil Kelkar, Ling Ma
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Patent number: 10593664Abstract: A semiconductor substrate has a main surface, a rear surface, an active device region, and an inactive region adjacent the active device region. Doped source, body, drift and drain regions, and electrically conductive gate and field electrodes are disposed in the active device region. The gate electrode is configured to control an electrical connection between the source and drain regions. The field electrode is adjacent to the drift region. An intermetal dielectric layer is disposed on the main surface, an electrically conductive source pad is formed in a first metallization layer that is formed on the intermetal dielectric layer. A resistor is connected between the source pad and the field electrode. The resistor includes an electrically conductive resistance section that is disposed in a resistor trench. The resistor trench is formed within the inactive region and is electrically isolated from every active device within the active device region.Type: GrantFiled: December 27, 2016Date of Patent: March 17, 2020Assignee: Infineon Technologies Americas Corp.Inventors: Hugo Burke, Kapil Kelkar, Ling Ma
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Patent number: 10388591Abstract: According to an embodiment of a method for fabricating a trench field-effect transistor (trench FET), the method includes: the method includes: patterning a contact pad from a first metal layer situated over a surface of an active die; forming a dielectric layer over the contact pad; patterning the dielectric layer to form a plurality of dielectric islands spaced apart from one another by respective voids; and forming a second metal layer between and over the plurality of dielectric islands so as to substantially fill the respective voids. The contact pad, plurality of dielectric islands, and second metal layer provide the reliable and robust electrical contact.Type: GrantFiled: May 2, 2017Date of Patent: August 20, 2019Assignee: Infineon Technologies Americas Corp.Inventor: Hugo Burke
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Patent number: 10236246Abstract: A semiconductor device includes a crack propagation prevention structure. The crack propagation prevention structure is located at an edge region of a wiring layer stack located on a semiconductor substrate of the semiconductor device. Furthermore, the crack propagation prevention structure laterally surrounds at least one wiring structure located within the wiring layer stack. Additionally, the semiconductor device includes an insulation trench extending into the semiconductor substrate. The insulation trench comprises at least an insulation layer electrically insulating the crack propagation prevention structure from the semiconductor substrate. The crack propagation prevention structure extends vertically at least from a surface of the wiring layer stack to the insulation trench.Type: GrantFiled: July 14, 2017Date of Patent: March 19, 2019Assignee: Infineon Technologies Americas Corp.Inventor: Hugo Burke
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Publication number: 20180182750Abstract: A semiconductor substrate has a main surface, a rear surface, an active device region, and an inactive region adjacent the active device region. Doped source, body, drift and drain regions, and electrically conductive gate and field electrodes are disposed in the active device region. The gate electrode is configured to control an electrical connection between the source and drain regions. The field electrode is adjacent to the drift region. An intermetal dielectric layer is disposed on the main surface, an electrically conductive source pad is formed in a first metallization layer that is formed on the intermetal dielectric layer. A resistor is connected between the source pad and the field electrode. The resistor includes an electrically conductive resistance section that is disposed in a resistor trench. The resistor trench is formed within the inactive region and is electrically isolated from every active device within the active device region.Type: ApplicationFiled: December 27, 2016Publication date: June 28, 2018Inventors: Hugo Burke, Kapil Kelkar, Ling Ma
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Patent number: 9966464Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.Type: GrantFiled: March 13, 2017Date of Patent: May 8, 2018Assignee: Infineon Technologies Americas Corp.Inventors: Kapil Kelkar, Timothy D. Henson, Ling Ma, Mary Bigglestone, Adam Amali, Hugo Burke, Robert Haase
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Publication number: 20180019204Abstract: A semiconductor device includes a crack propagation prevention structure. The crack propagation prevention structure is located at an edge region of a wiring layer stack located on a semiconductor substrate of the semiconductor device. Furthermore, the crack propagation prevention structure laterally surrounds at least one wiring structure located within the wiring layer stack. Additionally, the semiconductor device includes an insulation trench extending into the semiconductor substrate. The insulation trench comprises at least an insulation layer electrically insulating the crack propagation prevention structure from the semiconductor substrate. The crack propagation prevention structure extends vertically at least from a surface of the wiring layer stack to the insulation trench.Type: ApplicationFiled: July 14, 2017Publication date: January 18, 2018Inventor: Hugo BURKE
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Patent number: 9818743Abstract: Disclosed is a power semiconductor device that includes a plurality of source trenches and adjacent source regions. The plurality of source trenches extend from a top surface of a semiconductor substrate into the semiconductor substrate. The power semiconductor device further includes a plurality of gate trenches that extend from the top of the semiconductor substrate into the semiconductor substrate, and are arranged in hexagonal or zigzag patterns. A contiguous formation is created by the plurality of gate trenches, and the plurality of gate trenches separate the plurality of source trenches from one another.Type: GrantFiled: June 9, 2014Date of Patent: November 14, 2017Assignee: INFINEON TECHNOLOGIES AMERICAS CORP.Inventors: Kapil Kelkar, Timothy D. Henson, Ling Ma, Hugo Burke, Niraj Ranjan, Alain Charles
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Patent number: 9812538Abstract: A semiconductor structure includes a semiconductor substrate having a gate electrode in a gate trench, a buried bus in the semiconductor substrate, the buried bus having a bus conductive filler in a bus trench, where the bus conductive filler is electrically coupled to the gate electrode. The bus conductive filler is surrounded by the gate electrode. The gate trench intersects the bus trench in the semiconductor substrate. The gate electrode includes polysilicon. The bus conductive filler includes tungsten. The semiconductor structure also includes an adhesion promotion layer interposed between the bus conductive filler and the gate electrode, where the adhesion promotion layer includes titanium and titanium nitride. The semiconductor structure also includes a dielectric layer covering the gate electrode over the semiconductor substrate, where the buried bus has a coplanar top surface with the dielectric layer.Type: GrantFiled: December 1, 2015Date of Patent: November 7, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Hugo Burke, Ling Ma
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Patent number: 9761550Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.Type: GrantFiled: April 13, 2016Date of Patent: September 12, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Robert Montgomery, Hugo Burke, Phillip Parsonage, Susan Johns, David Paul Jones
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Publication number: 20170236771Abstract: In one implementation, a reliable and robust electrical contact includes a contact pad patterned from a first metal layer situated over a surface of an active die, and multiple dielectric islands situated over the contact pad. The dielectric islands are spaced apart from one another by respective segments of a second metal layer formed between and over the dielectric islands. The contact pad, the dielectric islands, and the second metal layer provide the reliable and robust electrical contact.Type: ApplicationFiled: May 2, 2017Publication date: August 17, 2017Inventor: Hugo Burke
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Publication number: 20170213909Abstract: According to an embodiment of a method for fabricating a trench field-effect transistor (trench FET), the method includes: forming a trench in a semiconductor substrate of a first conductivity type, the trench including sidewalls which taper from a wider, top portion of the trench to a narrower, bottom portion of the trench; forming a gate dielectric in the trench, the gate dielectric having substantially the same thickness in the wider, top portion of the trench as in the narrower, bottom portion of the trench; forming a gate electrode in the trench and separated from the semiconductor substrate by the gate dielectric; and forming a channel region of a second conductivity type in the semiconductor substrate after forming the trench and the gate dielectric, the channel region being disposed adjacent the trench. Trench FETs formed by the method are also disclosed.Type: ApplicationFiled: April 10, 2017Publication date: July 27, 2017Inventors: Timothy D. Henson, Ling Ma, Hugo Burke, David P. Jones, Kapil Kelkar, Niraj Ranjan, Igor Bol
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Publication number: 20170186861Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Kapil Kelkar, Timothy D. Henson, Ling Ma, Mary Bigglestone, Adam Amali, Hugo Burke, Robert Haase
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Patent number: 9673287Abstract: In one implementation, a reliable and robust electrical contact includes a contact pad patterned from a first metal layer situated over a surface of an active die, and multiple dielectric islands situated over the contact pad. The dielectric islands are spaced apart from one another by respective segments of a second metal layer formed between and over the dielectric islands. The contact pad, the dielectric islands, and the second metal layer provide the reliable and robust electrical contact.Type: GrantFiled: November 17, 2015Date of Patent: June 6, 2017Assignee: Infineon Technologies Americas Corp.Inventor: Hugo Burke
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Publication number: 20170154970Abstract: A semiconductor structure includes a semiconductor substrate having a gate electrode in a gate trench, a buried bus in the semiconductor substrate, the buried bus having a bus conductive filler in a bus trench, where the bus conductive filler is electrically coupled to the gate electrode. The bus conductive filler is surrounded by the gate electrode. The gate trench intersects the bus trench in the semiconductor substrate. The gate electrode includes polysilicon. The bus conductive filler includes tungsten. The semiconductor structure also includes an adhesion promotion layer interposed between the bus conductive filler and the gate electrode, where the adhesion promotion layer includes titanium and titanium nitride. The semiconductor structure also includes a dielectric layer covering the gate electrode over the semiconductor substrate, where the buried bus has a coplanar top surface with the dielectric layer.Type: ApplicationFiled: December 1, 2015Publication date: June 1, 2017Inventors: Hugo Burke, Ling Ma
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Patent number: 9653597Abstract: Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.Type: GrantFiled: May 20, 2010Date of Patent: May 16, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Timothy D. Henson, Ling Ma, Hugo Burke, David P. Jones, Kapil Kelkar, Niraj Ranjan, Igor Bol
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Patent number: 9627328Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.Type: GrantFiled: September 30, 2015Date of Patent: April 18, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Kapil Kelkar, Timothy D. Henson, Ling Ma, Mary Bigglestone, Adam Amali, Hugo Burke, Robert Haase
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Patent number: 9620583Abstract: A power semiconductor device is disclosed. The power semiconductor device includes a source region in a body region, a gate trench adjacent to the source region, and a source trench electrically coupled to the source region. The source trench includes a source trench conductive filler surrounded by a source trench dielectric liner, and extends into a drift region. The power semiconductor device includes a source trench implant below the source trench and a drain region below the drift region, where the source trench implant has a conductivity type opposite that of the drift region. The power semiconductor device may also include a termination trench adjacent to the source trench, where the termination trench includes a termination trench conductive filler surrounded by a termination trench dielectric liner. The power semiconductor device may also include a termination trench implant below the termination trench.Type: GrantFiled: September 16, 2015Date of Patent: April 11, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Kapil Kelkar, Timothy D. Henson, Ling Ma, Mary Bigglestone, Adam Amali, Hugo Burke, Robert Haase
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Publication number: 20160233185Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.Type: ApplicationFiled: April 13, 2016Publication date: August 11, 2016Inventors: Robert Montgomery, Hugo Burke, Phillip Parsonage, Susan Johns, David Paul Jones