Method for Fabricating a Shallow and Narrow Trench FET
According to an embodiment of a method for fabricating a trench field-effect transistor (trench FET), the method includes: forming a trench in a semiconductor substrate of a first conductivity type, the trench including sidewalls which taper from a wider, top portion of the trench to a narrower, bottom portion of the trench; forming a gate dielectric in the trench, the gate dielectric having substantially the same thickness in the wider, top portion of the trench as in the narrower, bottom portion of the trench; forming a gate electrode in the trench and separated from the semiconductor substrate by the gate dielectric; and forming a channel region of a second conductivity type in the semiconductor substrate after forming the trench and the gate dielectric, the channel region being disposed adjacent the trench. Trench FETs formed by the method are also disclosed.
1. Field of the Invention
The present invention is generally in the field of semiconductors. More specifically, the present invention is in the field of fabrication of transistors.
2. Background Art
Power semiconductor devices, such as field-effect transistors (FETs) are widely used in a variety of electronic devices and systems. Examples of such electronic devices and systems are power converters, such as DC to DC converters, in which vertically conducting trench type silicon FETs, for instance, may be implemented as power switches. In power converters, power losses within the power switches, as well as factors affecting switching speed, are becoming increasingly important. For example, for optimal performance it is desirable to reduce overall gate charge Qg, gate resistance Rg, and ON-resistance Rdson of the power switches.
Optimizing Rdson in a vertical trench FET, for example, may require carefully controlling the length of the channel. That is to say, implementation of a vertical trench FET having a short channel may improve the Rdson characteristic of the device. However, conventional methods of forming vertical trench FETs can undesirably affect channel length rendering a short channel unachievable and the channel length uncontrollable. For example, conventional methods can expose dopants, used to form the channel, to high temperature processes, thereby uncontrollably increasing channel length. Moreover, the conventional vertical trench FET requires deep trenches to, for example, counter the lack of control over the channel length.
Thus, there is a need for a method that can provide trench FETs while overcoming the drawbacks and deficiencies in the art.
SUMMARY OF THE INVENTIONA method for fabricating a shallow and narrow trench field-effect transistor (trench FET) and related structures, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
The present invention is directed to a method for fabricating a shallow and narrow trench field-effect transistor (trench FET) and related structures. Although the invention is described with respect to specific embodiments, the principles of the invention, as defined by the claims appended herein, can obviously be applied beyond the specifically described embodiments of the invention described herein. Moreover, in the description of the present invention, certain details have been left out in order to not obscure the inventive aspects of the invention. The details left out are within the knowledge of a person of ordinary skill in the art.
The drawings in the present application and their accompanying detailed description are directed to merely example embodiments of the invention. To maintain brevity, other embodiments of the invention, which use the principles of the present invention, are not specifically described in the present application and are not specifically illustrated by the present drawings. It should be borne in mind that, unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are not intended to correspond to actual relative dimensions.
As shown in
Also shown in
As shown in
As stated above, in the present example, transistors 102a and 102b have similar dimensions. Thus, as shown in
The formation of semiconductor device 100 is subject to significant constraints, which can degrade device performance and characteristics. For example, in forming transistor 102a, source depth 119 and channel length 120 are subject to significant constraints, which prevent formation of a short channel device. Thus, reduction of Rdson is significantly limited in semiconductor device 100.
In forming transistor 102a, a semiconductor substrate is doped with, for example, P type dopants, to form channel regions 106. N type source regions 108 can be formed before or after formation of the transistor gate. When trench 110, gate dielectric 116, and gate electrode 118 are formed in the semiconductor substrate, the semiconductor substrate is exposed to significant temperatures, which can undesirably drive the dopants and can render channel length 120 uncontrollable in semiconductor device 100. For example, channel length 120 (and source depth 119, if source regions 108 are formed prior to gate formation) can be driven to an undesirable depth, preventing a relatively short channel length 120 and requiring a deep trench 110.
Forming a gate dielectric can comprise a high temperature process. Furthermore, including a thick bottom oxide, for example thick bottom oxide 140, requires additional processing steps, which can increase exposure of dopants to high temperatures. Thus, because gate dielectric 116 includes thick bottom oxide 140, the semiconductor substrate can be exposed to additional high temperatures, further increasing channel length 120 in semiconductor device 100, thereby hindering formation of a short channel length 120 and a shallow trench 110. Forming thick bottom oxide 140 can further complicate formation of semiconductor device 100, for example, by requiring additional processing steps and increasing manufacturing costs.
Forming transistor 102a with recess 117 can also introduce significant constraints in forming semiconductor device 100. In transistor 102a, recess 117 prevents shorting between gate electrode 118 and source regions 108 and can have a depth of approximately 0.15 microns. The depth of recess 117 can be difficult to control in formation of semiconductor device 100. Thus, reducing source depth 119, introduces considerable risk of gate electrode 118 falling below source regions 108, which would significantly degrade device performance. As such, source depth 119 cannot be significantly reduced in order to prevent gate electrode 118 from falling below source regions 108, thereby hindering formation of a short channel length 120 and a shallow trench 110.
The present invention provides a trench field-effect transistor (trench FET) and a method for fabricating the same. The method can be used to form a shallow and narrow trench FET having improved device performance characteristics, such as Rdson, not achievable in conventional semiconductor devices, by reducing or eliminating significant constraints imposed by conventional methods.
While steps 210 through 250 indicated in flowchart 200 are sufficient to describe embodiments of the present invention, other embodiments of the invention may utilize steps different from those shown in flowchart 200, or may comprise more, or fewer, steps. For example, while the method of flowchart 200 is for an N channel device, it will be appreciated that the present invention can also provide for a P channel device. Furthermore, the sequence of steps 210 through 250 is not limited by flowchart 200. For example, while flowchart 200 shows step 250 occurring after step 240, in other embodiments step 250 can occur before step 240.
Exemplary shallow and narrow trench FETs, which can be fabricated according the present invention, will be described with respect to
Referring now to step 210 of
Trench 310, which can correspond to the trench formed in step 210, includes sidewalls 312 and bottom portion 314. As shown in
Now referring to step 220 of
As shown in
In semiconductor device 400, bottom implanted region 430 can account for process variations, which can form a shallower trench 410 than desired. For example, without bottom implanted region 430, bottom portion 414 may be formed too shallow to sufficiently contact drift region 404. Thus, bottom implanted region 430 can enable a shallower trench 410 by maintaining contact between bottom portion 414 and drift region 404 with process variations.
Furthermore, because trench FET 402a includes gate dielectric 416, formed without a thick bottom oxide, bottom implanted region 430 is not exposed to additional process temperatures used to form the thick bottom oxide. These additional process temperatures can prevent formation of an effective and controllable bottom implanted region, for example, in semiconductor device 100, by significantly driving deeper the dopants used to form the bottom implanted region. Controlling dopants is increasingly important as device dimensions are reduced, for example, in forming shallow and narrow trench FETs 402a and 402b.
Referring to step 230 of
Gate dielectric 316 can be formed without a thick bottom oxide in trench 310. As discussed above, including gate dielectric 116 having thick bottom oxide 140 can reduce gate to drain charge Qgd. However, also discussed above, forming thick bottom oxide 140 can introduce significant constraints in device fabrication, particularly in fabricating shallow and narrow trench FETs. Thus, in semiconductor device 300, sidewalls 312 of trench 310 taper into a narrower bottom portion 314. Alternatively, the entire trench 310 can be formed narrowly (with substantially the same small width) from top to bottom or with a slightly tapered bottom portion. However, including a narrower bottom portion 314 in forming trench FET 302a, according to the present invention, can substantially reduce gate to drain charge Qgd and overall gate charge Qg, thereby significantly enhancing device performance. Thus, trench FETs 302a and 402a, for example, can be formed without a thick bottom oxide in respective trenches 310 and 410, while achieving low gate to drain charge Qgd.
Referring now to step 240 of
Forming gate electrode 318 coplanar with a top surface of the semiconductor substrate can prevent short circuit between gate electrode 318 and source regions 308 in trench FET 302a. Thus, as shown in
Referring to step 250 of
In contrast to conventional methods, in forming, for example, source regions 308 and channel regions 306, the doped semiconductor regions are exposed to significantly lower temperatures and are saved from higher temperature processes that were associated with trench formation and the related dielectric growth and deposition in the conventional process flow. Thus, the present invention prevents an increase in the depth of source regions 308 and channel regions 306 that would otherwise result from higher temperature processes in the conventional approach. Thus, the present invention provides for reduced source depth 319 and channel length 320, enabling a shorter channel length 320 and a shallower trench 310 in semiconductor device 300.
For example, in one embodiment, the semiconductor substrate is doped to form channel regions 306 after forming gate dielectric 316. Thus, the doped semiconductor substrate may not be exposed to, for example, high thermal oxidation temperatures. As stated previously, in one embodiment step 250 can be performed after step 230, but before step 240, of flowchart 200. However, in the embodiment shown in
Thus, in one specific example, in trench FET 302a, source depth 319 can be, for example, 0.15 microns and channel length 320 can be, for example, approximately 0.3 to 0.45 microns. By way of example, the depth of trench 310 can be approximately 0.6 to 0.8 microns. As such, ON-resistance Rdson can be significantly reduced compared to, for example, transistor 102a in
After completion of step 250, additional steps can be performed in order to form semiconductor device 300 in
Thus, as discussed above, in the embodiments of
Claims
1-20. (canceled)
21. A method for fabricating a trench field-effect transistor (trench FET), the method comprising:
- forming a trench in a semiconductor substrate of a first conductivity type, the trench including sidewalls which taper from a wider, top portion of the trench to a narrower, bottom portion of the trench;
- forming a gate dielectric in the trench, the gate dielectric having substantially the same thickness in the wider, top portion of the trench as in the narrower, bottom portion of the trench;
- forming a gate electrode in the trench and separated from the semiconductor substrate by the gate dielectric; and
- forming a channel region of a second conductivity type in the semiconductor substrate after forming the trench and the gate dielectric, the channel region being disposed adjacent the trench.
22. The method of claim 21, wherein the channel region is formed by dopant implantation.
23. The method of claim 21, further comprising:
- forming a bottom implanted region of the first conductivity type surrounding the narrower, bottom portion of the trench before forming the gate dielectric in the trench, the bottom implanted region having a dopant concentration greater than the dopant concentration of the semiconductor substrate, the narrower, bottom portion of the trench being disposed in the bottom implanted region.
24. The method of claim 21, wherein the gate electrode is coplanar with a top surface of the semiconductor substrate.
25. The method of claim 24, wherein the gate electrode is made coplanar with a top surface of the semiconductor substrate by chemical mechanical polishing of the top surface.
26. The method of claim 21, further comprising:
- forming a source region of the first conductivity type in the semiconductor substrate adjacent the trench, after forming the trench and the gate dielectric.
27. The method of claim 26, further comprising:
- forming a drift region of the first conductivity type in the semiconductor substrate, the drift region being separated from the source region by the channel region.
28. The method of claim 27, wherein the narrower, bottom portion of the trench is disposed in the drift region.
29. The method of claim 26, further comprising:
- forming a drift region of the first conductivity type in the semiconductor substrate below the channel region so that the source region is separated from the drift region by the channel region; and
- forming a bottom implanted region of the first conductivity type surrounding the narrower, bottom portion of the trench before forming the gate dielectric in the trench, the bottom implanted region being disposed in the drift region and having a dopant concentration greater than the dopant concentration of the semiconductor substrate,
- wherein the narrower, bottom portion of the trench is disposed in the bottom implanted region.
30. The method of claim 26, wherein the gate electrode is coplanar with a top surface of the source region.
31. The method of claim 26, further comprising:
- forming a recessed region in the semiconductor substrate which extends through the source region and into the channel region,
- wherein a top surface of the gate electrode is disposed above a bottom surface of the recessed region.
32. The method of claim 26, wherein a depth of the source region is 0.15 microns or less, wherein a length of the channel region is between 0.3 to 0.45 microns, and wherein a depth of the trench is between 0.6 to 0.8 microns.
33. The method of claim 26, further comprising:
- forming a first dielectric portion over the source region;
- forming a second dielectric portion over the trench; and
- forming a third dielectric portion over the first and the second dielectric portions.
34. The method of claim 33, further comprising:
- forming a source contact material over the semiconductor substrate,
- wherein the second and the third dielectric portions insulate the gate electrode from the source contact material,
- wherein the first and the third dielectric portions separate the source contact material from a top surface of the source region,
- wherein the source contact material contacts a side face of the source region uncovered by the first and the third dielectric portions.
35. The method of claim 21, wherein the semiconductor substrate is doped to form the channel region after forming the gate electrode.
36. A trench field-effect transistor (trench FET), comprising:
- a trench formed in a semiconductor substrate of a first conductivity type, the trench including sidewalls which taper from a wider, top portion of the trench to a narrower, bottom portion of the trench;
- a gate dielectric formed in the trench, the gate dielectric having substantially the same thickness in the wider, top portion of the trench as in the narrower, bottom portion of the trench;
- a gate electrode formed in the trench and separated from the semiconductor substrate by the gate dielectric; and
- a channel region of a second conductivity type formed in the semiconductor substrate, the channel region being disposed adjacent the trench.
37. The trench FET of claim 36, further comprising a bottom implanted region of the first conductivity type surrounding the narrower, bottom portion of the trench, wherein the bottom implanted region has a dopant concentration greater than the dopant concentration of the semiconductor substrate, and wherein the narrower, bottom portion of the trench is disposed in the bottom implanted region.
38. The trench FET of claim 36, wherein the gate electrode is coplanar with a top surface of the semiconductor substrate.
39. The trench FET of claim 36, further comprising a source region of the first conductivity type formed in the semiconductor substrate adjacent the trench.
40. The trench FET of claim 39, further comprising a drift region of the first conductivity type formed in the semiconductor substrate, wherein the drift region is separated from the source region by the channel region.
41. The trench of claim 40, wherein the narrower, bottom portion of the trench is disposed in the drift region.
42. The trench FET of claim 39, further comprising:
- a drift region of the first conductivity type formed in the semiconductor substrate below the channel region; and
- a bottom implanted region of the first conductivity type surrounding the narrower, bottom portion of the trench,
- wherein the source region is separated from the drift region by the channel region,
- wherein the bottom implanted region is disposed in the drift region and has a dopant concentration greater than the dopant concentration of the semiconductor substrate,
- wherein the narrower, bottom portion of the trench is disposed in the bottom implanted region.
43. The trench FET of claim 42, wherein the gate electrode is coplanar with a top surface of the source region.
44. The trench FET of claim 42, further comprising a recessed region in the semiconductor substrate which extends through the source region and into the channel region, wherein a top surface of the gate electrode is disposed above a bottom surface of the recessed region.
45. The trench of claim 42, wherein a depth of the source region is 0.15 microns or less, wherein a length of the channel region is between 0.3 to 0.45 microns, and wherein a depth of the trench is between 0.6 to 0.8 microns.
46. The trench FET of claim 36, further comprising:
- a first dielectric portion formed over the source region;
- a second dielectric portion formed over the trench; and
- a third dielectric portion formed over the first and the second dielectric portions.
47. The trench FET of claim 46, further comprising:
- a source contact material formed over the semiconductor substrate,
- wherein the second and the third dielectric portions insulate the gate electrode from the source contact material,
- wherein the first and the third dielectric portions separate the source contact material from a top surface of the source region,
- wherein the source contact material contacts a side face of the source region uncovered by the first and the third dielectric portions.
Type: Application
Filed: Apr 10, 2017
Publication Date: Jul 27, 2017
Inventors: Timothy D. Henson (Torrance, CA), Ling Ma (Redondo Beach, CA), Hugo Burke (Llantrisant), David P. Jones (Penarth), Kapil Kelkar (Torrance, CA), Niraj Ranjan (El Segundo, CA), Igor Bol (Topanga, CA)
Application Number: 15/483,544