Patents by Inventor Hugo Santiago Carrer
Hugo Santiago Carrer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10841013Abstract: A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.Type: GrantFiled: November 5, 2019Date of Patent: November 17, 2020Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Hugo Santiago Carrer, Mario Rafael Hueda, German Cesar Augusto Luna, Carl Grace
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Patent number: 10763972Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.Type: GrantFiled: November 25, 2019Date of Patent: September 1, 2020Assignee: INPHI CORPORATIONInventors: Mario Rafael Hueda, Mauro Marcelo Bruni, Federico Nicolas Paredes, Hugo Santiago Carrer, Diego Ernesto Crivelli, Oscar Ernesto Agazzi, Norman L. Swenson, Seyedmohammadreza Motaghiannezam
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Patent number: 10742327Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: GrantFiled: October 11, 2019Date of Patent: August 11, 2020Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Adrián Ulises Morales, Martin Ignacio Del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro Marcelo Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, María Laura Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
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Publication number: 20200092011Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.Type: ApplicationFiled: November 25, 2019Publication date: March 19, 2020Inventors: Mario Rafael HUEDA, Mauro Marcelo BRUNI, Federico Nicolas PAREDES, Hugo Santiago CARRER, Diego Ernesto CRIVELLI, Oscar Ernesto AGAZZI, Norman L. SWENSON, Seyedmohammadreza MOTAGHIANNEZAM
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Publication number: 20200067600Abstract: A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.Type: ApplicationFiled: November 5, 2019Publication date: February 27, 2020Inventors: Oscar Ernesto AGAZZI, Diego Ernesto CRIVELLI, Hugo Santiago CARRER, Mario Rafael HUEDA, German Cesar Augusto LUNA, Carl GRACE
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Publication number: 20200044744Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: ApplicationFiled: October 11, 2019Publication date: February 6, 2020Inventors: Oscar Ernesto AGAZZI, Diego Ernesto CRIVELLI, Paul VOOIS, Ramiro Rogelio LOPEZ, Jorge Manuel FINOCHIETTO, Norman L. SWENSON, Mario Rafael HUEDA, Hugo Santiago CARRER, Vadim GUTNIK, Adrián Ulises MORALES, Martin Ignacio DEL BARCO, Martin Carlos ASINARI, Federico Nicolas PAREDES, Alfredo Javier TADDEI, Mauro Marcelo BRUNI, Damian Alfonso MORERO, Facundo Abel Alcides RAMOS, María Laura FERSTER, Elvio Adrian SERRANO, Pablo Gustavo QUIROGA, Roman Antonio ARENAS, Matias German SCHNIDRIG, Alejandro Javier SCHWOYKOSKI
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Patent number: 10530493Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.Type: GrantFiled: December 6, 2018Date of Patent: January 7, 2020Assignee: INPHI CORPORATIONInventors: Mario Rafael Hueda, Mauro Marcelo Bruni, Federico Nicolas Paredes, Hugo Santiago Carrer, Diego Ernesto Crivelli, Oscar Ernesto Agazzi, Norman L. Swenson, Seyedmohammadreza Motaghiannezam
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Patent number: 10505638Abstract: A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.Type: GrantFiled: September 4, 2018Date of Patent: December 10, 2019Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Hugo Santiago Carrer, Mario Rafael Hueda, German Cesar Augusto Luna, Carl Grace
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Patent number: 10491304Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: GrantFiled: November 29, 2018Date of Patent: November 26, 2019Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Adrián Ulises Morales, Martin Ignacio Del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro Marcelo Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, Maria Laura Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
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Publication number: 20190115984Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.Type: ApplicationFiled: December 6, 2018Publication date: April 18, 2019Inventors: Mario Rafael HUEDA, Mauro Marcelo BRUNI, Federico Nicolas PAREDES, Hugo Santiago CARRER, Diego Ernesto CRIVELLI, Oscar Ernesto AGAZZI, Norman L. SWENSON, Seyedmohammadreza MOTAGHIANNEZAM
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Publication number: 20190109646Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: ApplicationFiled: November 29, 2018Publication date: April 11, 2019Inventors: Oscar Ernesto AGAZZI, Diego Ernesto CRIVELLI, Paul VOOIS, Ramiro Rogelio LOPEZ, Jorge Manuel FINOCHIETTO, Norman L. SWENSON, Mario Rafael HUEDA, Hugo Santiago CARRER, Vadim GUTNIK, Adrián Ulises MORALES, Martin Ignacio DEL BARCO, Martin Carlos ASINARI, Federico Nicolas PAREDES, Alfredo Javier TADDEI, Mauro Marcelo BRUNI, Damian Alfonso MORERO, Facundo Abel Alcides RAMOS, María Laura FERSTER, Elvio Adrian SERRANO, Pablo Gustavo QUIROGA, Roman Antonio ARENAS, Matias German SCHNIDRIG, Alejandro Javier SCHWOYKOSKI
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Publication number: 20190020415Abstract: A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.Type: ApplicationFiled: September 4, 2018Publication date: January 17, 2019Inventors: Oscar Ernesto AGAZZI, Diego Ernesto CRIVELLI, Hugo Santiago CARRER, Mario Rafael HUEDA, German Cesar Augusto LUNA, Carl GRACE
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Patent number: 10181908Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.Type: GrantFiled: December 12, 2017Date of Patent: January 15, 2019Assignee: INPHI CORPORATIONInventors: Mario Rafael Hueda, Mauro Marcelo Bruni, Federico Nicolas Paredes, Hugo Santiago Carrer, Diego Ernesto Crivelli, Oscar Ernesto Agazzi, Norman L. Swenson, Seyedmohammadreza Motaghiannezam
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Patent number: 10177851Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: GrantFiled: July 12, 2017Date of Patent: January 8, 2019Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Adrián Ulises Morales, Martin Ignacio Del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro Marcelo Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, María Laura Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
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Patent number: 10097273Abstract: A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.Type: GrantFiled: December 12, 2017Date of Patent: October 9, 2018Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Hugo Santiago Carrer, Mario Rafael Hueda, German Cesar Augusto Luna, Carl Grace
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Patent number: 10056981Abstract: A receiver for fiber optic communications.Type: GrantFiled: March 14, 2018Date of Patent: August 21, 2018Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Hugo Santiago Carrer, Mario Rafael Hueda, Martin Ignacio Del Barco, Pablo Gianni, Ariel Pola, Elvio Adrian Serrano, Alfredo Javier Taddei, Mario Alejandro Castrillon, Martin Serra, Ramiro Matteoda
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Patent number: 10038506Abstract: A transceiver for fiber optic communications. The transceiver can include a transmitter module having a transmitter host interface configured to receive an input host signal; a transmitter framer configured to frame the input host signal and to generate a framed host signal; and a transmitter coder configured to encode the framed host signal to generate an encoded host signal for transmission over a communication channel. The transceiver can also include a receiver module having a bulk chromatic dispersion, fiber length estimation, and coarse carrier recovery circuit configured to equalize a digital input ingress signal to generate an equalized ingress signal; a receiver framer configured to frame the equalized ingress signal to generate a framed ingress signal; and a receiver host interface configured to output the framed ingress signal. The receiver host interface is compatible with a framing protocol of the receiver framer.Type: GrantFiled: November 1, 2017Date of Patent: July 31, 2018Assignee: INPHI CORPORATIONInventors: Diego Ernesto Crivelli, Mario Rafael Hueda, Hugo Santiago Carrer, Jeffrey Zachan, Vadim Gutnik, Martin Ignacio Del Barco, Ramiro Rogelio Lopez, Shih Cheng Wang, Geoffrey O. Hatcher, Jorge Manuel Finochietto, Michael Yeo, Andre Chartrand, Norman L. Swenson, Paul Voois, Oscar Ernesto Agazzi
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Publication number: 20180205466Abstract: A receiver for fiber optic communications.Type: ApplicationFiled: March 14, 2018Publication date: July 19, 2018Inventors: Oscar Ernesto AGAZZI, Diego Ernesto CRIVELLI, Hugo Santiago CARRER, Mario Rafael HUEDA, Martin Ignacio DEL BARCO, Pablo GIANNI, Ariel POLA, Elvio Adrian SERRANO, Alfredo Javier TADDEI, Mario Alejandro CASTRILLON, Martin SERRA, Ramiro MATTEODA
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Patent number: 9960855Abstract: A receiver for fiber optic communications.Type: GrantFiled: October 17, 2017Date of Patent: May 1, 2018Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Hugo Santiago Carrer, Mario Rafael Hueda, Martin Ignacio Del Barco, Pablo Gianni, Ariel Pola, Elvio Adrian Serrano, Alfredo Javier Taddei, Mario Alejandro Castrillon, Martin Serra, Ramiro Matteoda
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Publication number: 20180115369Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.Type: ApplicationFiled: December 12, 2017Publication date: April 26, 2018Inventors: Mario Rafael HUEDA, Mauro Marcelo BRUNI, Federico Nicolas PAREDES, Hugo Santiago CARRER, Diego Ernesto CRIVELLI, Oscar Ernesto AGAZZI, Norman L. SWENSON, Seyedmohammadreza MOTAGHIANNEZAM