Abstract: A method of forming a semiconductor device includes loading a first wafer and a second wafer into a wafer bonding system. A relative humidity within the wafer bonding system is measured a first time. After measuring the relative humidity, the relative humidity within the wafer bonding system may be adjusted to be within a desired range. When the relative humidity is within the desired range, the first wafer is bonded to the second wafer.

Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.

Abstract: A method of transferring semiconductor wafers and a semiconductor wafer support device including lift pins having a first end configured to contact a backside surface of the semiconductor wafer and at least one stress reduction feature. The stress reduction feature may be configured to reduce contact stress between the lift pins and the wafer.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.

Abstract: A method of forming a semiconductor device includes implanting dopants of a first conductivity type into a semiconductor substrate to form a first well, epitaxially growing a channel layer over the semiconductor substrate, forming a fin from the second semiconductor material, and forming a gate structure over a channel region of the fin. The semiconductor substrate includes a first semiconductor material. Implanting the dopants may be performed at a temperature in a range of 150° C. to 500° C. The channel layer may include a second semiconductor material. The channel layer may be doped with dopants of the first conductivity type.

Abstract: FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.

Abstract: A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.

Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.

Abstract: In an embodiment, a wafer bonding system includes a chamber, a gas inlet and a gas outlet configured to control a pressure of the chamber to be in a range from 1×10?2 mbar to 1520 torr, a first wafer chuck having a first surface to support a first wafer, and a second wafer chuck having a second surface to support a second wafer, the second surface being opposite the first surface, the second wafer chuck and the first wafer chuck being movable relative to each other, wherein the second surface that supports the second wafer is divided into zones, wherein a vacuum pressure of each zone is controlled independently of other zones.

Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.

Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

Abstract: A method of forming a semiconductor device includes loading a first wafer and a second wafer into a wafer bonding system. A relative humidity within the wafer bonding system is measured a first time. After measuring the relative humidity, the relative humidity within the wafer bonding system may be adjusted to be within a desired range. When the relative humidity is within the desired range, the first wafer is bonded to the second wafer.

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.

Abstract: A semiconductor device may include a semiconductor fin, a source/drain region extending from the semiconductor fin, and a gate electrode over the semiconductor fin. The semiconductor fin may include a first well and a channel region over the first well. The first well may have a first dopant at a first dopant concentration and the channel region may have the first dopant at a second dopant concentration smaller than the first dopant concentration. The first dopant concentration may be in range from 1017 atoms/cm3 to 1019 atoms/cm3.

Abstract: Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

Abstract: A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.