Patents by Inventor Hui-Hsuan Wang

Hui-Hsuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090271458
    Abstract: A data storing method includes providing a storage space, receiving a data stream, establishing a cluster link when the data stream is stored into the storage space, and before the data stream is completely stored in the storage space, storing a cluster number of a specific node in the cluster link and information about a cluster following the specific node, and setting the content of the specific node as an EOF. A data storage system thereof can access a real-time data stream stored in the storage space, or release the occupied space in the storage space through deleting the file of the real-time data stream, even if the real-time data stream is interrupted abnormally during storage.
    Type: Application
    Filed: August 21, 2008
    Publication date: October 29, 2009
    Inventors: Zhe-Hong Guo, Hui-Hsuan Wang
  • Patent number: 6957244
    Abstract: This invention discloses a reduced-width, low-error multiplier that can be used in Digital Signal Processing (DSP). Specifically, this invention relates to a reduced-width, low-error multiplier capable of processing digital signals of communication systems such as a timing recovery circuit, a carrier recovery circuit, and a FIR filter, etc. This invention derives a binary compensation vector to compensate for the error caused by the reduction of area without any hardware overhead, and implements the compensation structure of an Array and a Booth multiplier to reduce hardware complexity.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: October 18, 2005
    Assignee: National Science Council
    Inventors: Shyh-Jye Jou, Hui-Hsuan Wang
  • Publication number: 20020032713
    Abstract: This invention purposes a reduced-width low-error multiplier that can be used in the DSP (Digital Signal Processing) approach of digital communication system. We derive a binary compensation vector to compensate the error caused by the reduction of area without any hardware overhead. We also implement the compensation structure in Array and Booth multiplier to reduce hardware complexity.
    Type: Application
    Filed: May 22, 2001
    Publication date: March 14, 2002
    Inventors: Shyh-Jye Jou, Hui-Hsuan Wang