Patents by Inventor Hui Jae Yoo

Hui Jae Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971394
    Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Todd R. Younkin, Eungnak Han, Jasmeet S. Chawla, Marie Krysak, Hui Jae Yoo, Tristan A. Tronic
  • Publication number: 20210091080
    Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).
    Type: Application
    Filed: March 28, 2018
    Publication date: March 25, 2021
    Inventors: Gilbert DEWEY, Ravi PILLARISETTY, Abhishek A. SHARMA, Aaron D. LILAK, Willy RACHMADY, Rishabh MEHANDRU, Kimin JUN, Anh PHAN, Hui Jae YOO, Patrick MORROW, Cheng-Ying HUANG
  • Publication number: 20210057413
    Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.
    Type: Application
    Filed: March 28, 2018
    Publication date: February 25, 2021
    Inventors: Gilbert DEWEY, Ravi PILLARISETTY, Jack T. KAVALIEROS, Aaron D. LILAK, Willy RACHMADY, Rishabh MEHANDRU, Kimin JUN, Anh PHAN, Hui Jae YOO, Patrick MORROW, Cheng-Ying HUANG, Matthew V. METZ
  • Publication number: 20210020502
    Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Inventors: HUI JAE YOO, TEJASWI K. INDUKURI, RAMANAN V. CHEBIAM, JAMES S. CLARKE
  • Publication number: 20200411365
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Cheng-Ying HUANG, Gilbert DEWEY, Jack T. KAVALIEROS, Aaron LILAK, Ehren MANNEBACH, Patrick MORROW, Anh PHAN, Willy RACHMADY, Hui Jae YOO
  • Publication number: 20200411315
    Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to manufacturing transistors that include a substrate, an epitaxial layer with a first side and a second side opposite the first side, where the first side and the second side of the epitaxial layer are substantially planar, where the second side of the epitaxial layer is substantially parallel to the first side, and where the first side of the epitaxial layer is directly coupled with a side of the substrate. In particular, the epitaxial layer may be adjacent to an oxide layer having a side that is substantially planar, where the second side of the epitaxial layer is adjacent to the side of the oxide layer, and the epitaxial layer was grown and the growth was constrained by the oxide layer.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Cheng-Ying HUANG, Gilbert DEWEY, Jack T. KAVALIEROS, Aaron LILAK, Ehren MANNEBACH, Patrick MORROW, Anh PHAN, Willy RACHMADY, Hui Jae YOO
  • Publication number: 20200411428
    Abstract: Disclosed herein are memory devices with a logic region between memory regions. For example, in some embodiments, a memory device may include: a first memory region; a second memory region; a logic region between the first memory region and the second memory region; and a metallization stack, wherein the first memory region is between the logic region and the metallization stack.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Anh Phan, Gilbert W. Dewey, Willy Rachmady, Prashant Majhi, Hui Jae Yoo, Cheng-Ying Huang, Ehren Mannebach
  • Publication number: 20200411526
    Abstract: A device is disclosed. The device includes a plurality of capacitors, a transistor connected to each of the plurality of capacitors, and a first dielectric layer and a second dielectric layer on respective adjacent sides of adjacent capacitors of the plurality of capacitors. The first dielectric layer and the second dielectric layer include a top portion and a bottom portion, the top portion of the first dielectric layer and the top portion of the second dielectric layer extend from respective directions and meet at a top portion of a space between the adjacent capacitors, the bottom portion of the first dielectric layer and the bottom portion of the second dielectric layer extend from respective directions and meet at a bottom portion of a space between the adjacent capacitors.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Abhishek SHARMA, Willy RACHMADY, Van H. LE, Travis W. LAJOIE, Urusa ALAAN, Hui Jae YOO, Sean MA, Aaron LILAK
  • Publication number: 20200411660
    Abstract: A device is disclosed. The device includes a gate conductor, a first source-drain region and a second source-drain region. The device includes a first air gap space between the first source-drain region and a first side of the gate conductor and a second air gap space between the second source-drain region and a second side of the gate conductor. A hard mask layer that includes holes is under the gate conductor, the first source-drain region, the second source-drain region and the air gap spaces. A planar dielectric layer is under the hard mask.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Kevin L. LIN, Tristan TRONIC
  • Publication number: 20200411430
    Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Anh PHAN, Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY, Rishabh MEHANDRU
  • Publication number: 20200411651
    Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Anh PHAN, Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY
  • Publication number: 20200411639
    Abstract: A device is disclosed. The device includes a first gate conductor, a first source-drain region adjacent a first side of the first gate conductor and a second source-drain region adjacent a second side of the first gate conductor, a second gate conductor below the first gate conductor, a third source-drain region below the first source-drain region and adjacent a first side of the second gate conductor and a fourth source-drain region below the second source-drain region and adjacent a second side of the second gate conductor, a first air gap space between the first source-drain region and a first side of the first gate conductor and a second air gap space between the second source-drain region and the second side of the second gate conductor. A planar dielectric layer is formed above the first gate conductor.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Anh PHAN, Hui Jae YOO, Patrick MORROW, Cheng-Ying HUANG, Willy RACHMADY, Gilbert DEWEY
  • Publication number: 20200403033
    Abstract: A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick R. Morrow, Hui Jae Yoo, Sean T. Ma, Scott B. Clendenning, Abhishek A. Sharma, Ehren Mannebach, Urusa Alaan
  • Publication number: 20200395386
    Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.
    Type: Application
    Filed: March 5, 2018
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
  • Publication number: 20200357687
    Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Sean KING, Hui Jae YOO, Sreenivas KOSARAJU, Timothy GLASSMAN
  • Patent number: 10832951
    Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Hui Jae Yoo, Tejaswi K. Indukuri, Ramanan V. Chebiam, James S. Clarke
  • Publication number: 20200313075
    Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Noriyuki SATO, Angeline SMITH, Tanay GOSAVI, Sasikanth MANIPATRUNI, Kaan OGUZ, Kevin O'Brien, Benjamin BUFORD, Tofizur RAHMAN, Rohan PATIL, Nafees KABIR, Michael CHRISTENSON, Ian YOUNG, Hui Jae YOO, Christopher WIEGAND
  • Publication number: 20200303238
    Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 24, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Rishabh MEHANDRU, Hui Jae YOO, Patrick MORROW, Kevin LIN
  • Publication number: 20200294998
    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Applicant: INTEL CORPORATION
    Inventors: AARON D. LILAK, EHREN MANNEBACH, ANH PHAN, RICHARD E. SCHENKER, STEPHANIE A. BOJARSKI, WILLY RACHMADY, PATRICK R. MORROW, JEFFERY D. BIELEFELD, GILBERT DEWEY, HUI JAE YOO
  • Publication number: 20200279850
    Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.
    Type: Application
    Filed: March 23, 2020
    Publication date: September 3, 2020
    Inventors: Abhishek SHARMA, Noriyuki SATO, Sarah ATANASOV, Huseyin Ekin SUMBUL, Gregory K. CHEN, Phil KNAG, Ram KRISHNAMURTHY, Hui Jae YOO, Van H. LE