Patents by Inventor Hui Ling Chen

Hui Ling Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240293407
    Abstract: Disclosed herein are methods for treating cancers in a subject. The method includes determining the plasma level of arginine in the subject, followed by administering to the subject an arginine deprivation therapy alone or in combination with an anti-cancer agent based on the determined plasma level of arginine. According to some embodiments of the present disclosure, the anti-cancer agent is selected from the group consisting of FOLFOX, docetaxel, cisplatin, pemetrexed, pembrolizumab, and a combination thereof.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 5, 2024
    Inventors: Hung-Wen CHEN, Shaw Tsen CHEN, Hui-Fen LIU, Chih-Ling KUO, Chiung-Fang SHIU
  • Patent number: 12027629
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: July 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Patent number: 11869854
    Abstract: A semiconductor structure in which the upper and lower semiconductor wafers are bonded by a hybrid bonding method is provided. The two semiconductor wafers each have discontinuous multiple metal traces or spiral coil-shaped metal traces. By hybrid bonding the two semiconductor wafers, multiple discontinuous metal traces are bonded together to form an inductance element with a continuous and non-intersecting path, or the two spiral coil-shaped metal traces are bonded together to form an inductance element. In this semiconductor structure, the inductance element formed by hybrid bonding has the advantage that the inductance value is easily adjusted.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: January 9, 2024
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chien-Ming Lai, Hui-Ling Chen, Zhi-Rui Sheng
  • Patent number: 11676682
    Abstract: Disclosed herein are methods of determining the sequence and/or positions of modified bases in a nucleic acid sample present in a circular molecule with a nucleic acid insert of known sequence comprising obtaining sequence data of at least two insert-sample units. In some embodiments, the methods comprise obtaining sequence data using circular pair-locked molecules. In some embodiments, the methods comprise calculating scores of sequences of the nucleic acid inserts by comparing the sequences to the known sequence of the nucleic acid insert, and accepting or rejecting repeats of the sequence of the nucleic acid sample according to the scores of one or both of the sequences of the inserts immediately upstream or downstream of the repeats of the sequence of the nucleic acid sample.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: June 13, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Chi Pan, Jenn-Yeh Fann, Chung-Fan Chiou, Hung-Chi Chien, Hui-Ling Chen
  • Publication number: 20230178657
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Application
    Filed: January 31, 2023
    Publication date: June 8, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Patent number: 11631771
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: April 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Publication number: 20230101900
    Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.
    Type: Application
    Filed: December 7, 2022
    Publication date: March 30, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Zhirui Sheng, Hui-Ling Chen, Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Chien En Hsu
  • Publication number: 20230052327
    Abstract: Described are methods and systems for calibrating simulation models to generate digital twins for physical entities. In some embodiments, a method includes receiving a plurality of datasets for a plurality of corresponding physical entities. A calibration request is enqueued to a calibration requests queue for each received dataset and includes information indicating a dataset and a corresponding physical entity. A plurality of calibration engines and a plurality of corresponding simulation clusters for generating a plurality of calibration results for a plurality of calibration requests dequeued from the calibration requests queue can be deployed.
    Type: Application
    Filed: November 3, 2022
    Publication date: February 16, 2023
    Applicant: PricewaterhouseCoopers LLP
    Inventors: Sai Phanindra VENKATAPURAPU, Mrinal Kanti MANDAL, Jerome Patrick OFFNER, Rakesh Vidya Chandra KAPILA, Gaurav DWIVEDI, Qian CHEN, Julia Hui-ling CHEN, Samuel Pierce BURNS, Paul M. D'ALESSANDRO
  • Patent number: 11557558
    Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: January 17, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhirui Sheng, Hui-Ling Chen, Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Chien En Hsu
  • Patent number: 11520957
    Abstract: Described are methods and systems for calibrating simulation models to generate digital twins for physical entities. In some embodiments, a method includes receiving a plurality of datasets for a plurality of corresponding physical entities. A calibration request is enqueued to a calibration requests queue for each received dataset and includes information indicating a dataset and a corresponding physical entity. A plurality of calibration engines and a plurality of corresponding simulation clusters for generating a plurality of calibration results for a plurality of calibration requests dequeued from the calibration requests queue can be deployed.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: December 6, 2022
    Assignee: PricewaterhouseCoopers LLP
    Inventors: Sai Phanindra Venkatapurapu, Mrinal Kanti Mandal, Jerome Patrick Offner, Rakesh Vidya Chandra Kapila, Gaurav Dwivedi, Qian Chen, Julia Hui-ling Chen, Samuel Pierce Burns, Paul M. D'Alessandro
  • Publication number: 20220384376
    Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. The outer bonding pad pattern includes first bonding pads, the inner bonding pad pattern includes second bonding pads, a density of the first bonding pads is greater than that of the second bonding pads. The first bonding pads of the outer bonding pad pattern is distributed to form a plurality of pad rings surrounding the inner bonding pad pattern, and the first bonding pads of the plurality of pad rings are aligned in a horizontal direction or a vertical direction.
    Type: Application
    Filed: August 4, 2022
    Publication date: December 1, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Ming-Tse Lin, Chung-Hsing Kuo, Hui-Ling Chen
  • Patent number: 11450633
    Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. A first bonding pad density of the outer bonding pad pattern is greater than a second bonding pad density of the inner bonding pad pattern.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: September 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Tse Lin, Chung-Hsing Kuo, Hui-Ling Chen
  • Publication number: 20220262752
    Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper passive component pattern, and the second layer includes a lower passive component pattern, wherein the upper passive component pattern is opposite to the lower passive component pattern. The first interconnection layer includes at least one first interconnect structure electrically connected on the upper passive component pattern. The second interconnection layer includes at least one second interconnect structure electrically connected on the passive component pattern. The first interconnect structure on the upper passive component pattern is hybrid bonded with the second interconnect structure on the lower passive component pattern. Therefore, the upper passive component pattern and the lower passive component pattern are joined by hybrid bonding to form a passive device.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Inventors: Chien-Ming Lai, Zhi-Rui Sheng, Hui-Ling Chen
  • Publication number: 20220189888
    Abstract: A semiconductor structure in which the upper and lower semiconductor wafers are bonded by a hybrid bonding method is provided. The two semiconductor wafers each have discontinuous multiple metal traces or spiral coil-shaped metal traces. By hybrid bonding the two semiconductor wafers, multiple discontinuous metal traces are bonded together to form an inductance element with a continuous and non-intersecting path, or the two spiral coil-shaped metal traces are bonded together to form an inductance element. In this semiconductor structure, the inductance element formed by hybrid bonding has the advantage that the inductance value is easily adjusted.
    Type: Application
    Filed: January 27, 2021
    Publication date: June 16, 2022
    Inventors: Chien-Ming Lai, Hui-Ling Chen, Zhi-Rui Sheng
  • Patent number: 11355431
    Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: June 7, 2022
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chien-Ming Lai, Zhi-Rui Sheng, Hui-Ling Chen
  • Patent number: 11354210
    Abstract: A system includes a host and a display. The host includes a programmable logic device (PIP), a baseboard management controller (BMC) and a switch. The PLD performs a power-on procedure based on a power-on sequence code, generates variable character information in the power-on procedure, and fills the variable character information into a variable field in a preset log text file to result in an updated log text file. When it is determined that the power-on procedure is not normally completed, the PLD controls the switch to switch to a debug mode, and transmits a video signal containing debug information corresponding to the updated log text file to the switch so that the video signal is outputted to the display.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: June 7, 2022
    Assignee: Mitac Computing Technology Corporation
    Inventors: Yen-Hui Chang, Hui-Ling Chen
  • Patent number: 11342465
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Grant
    Filed: January 3, 2021
    Date of Patent: May 24, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Publication number: 20220108946
    Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.
    Type: Application
    Filed: October 7, 2020
    Publication date: April 7, 2022
    Inventors: Chien-Ming Lai, Zhi-Rui Sheng, Hui-Ling Chen
  • Publication number: 20220005775
    Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.
    Type: Application
    Filed: August 4, 2020
    Publication date: January 6, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Zhirui Sheng, Hui-Ling Chen, Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Chien En Hsu
  • Publication number: 20210357556
    Abstract: Described are methods and systems for calibrating simulation models to generate digital twins for physical entities. In some embodiments, a method includes receiving a plurality of datasets for a plurality of corresponding physical entities. A calibration request is enqueued to a calibration requests queue for each received dataset and includes information indicating a dataset and a corresponding physical entity. A plurality of calibration engines and a plurality of corresponding simulation clusters for generating a plurality of calibration results for a plurality of calibration requests dequeued from the calibration requests queue can be deployed.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 18, 2021
    Applicant: PricewaterhouseCoopers LLP
    Inventors: Sai Phanindra VENKATAPURAPU, Mrinal Kanti MANDAL, Jerome Patrick OFFNER, Rakesh Vidya Chandra KAPILA, Gaurav DWIVEDI, Qian CHEN, Julia Hui-ling CHEN, Samuel Pierce BURNS, Paul M. D'ALESSANDRO