Patents by Inventor Hui-Min Huang

Hui-Min Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12237320
    Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
    Type: Grant
    Filed: November 21, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20240404989
    Abstract: A bonded assembly may be formed by providing a wafer comprising at least a first packaging substrate and a second packaging substrate in a low-oxygen ambient; performing a first plasma package-treatment process on the first semiconductor package in the low-oxygen ambient while performing a first substrate-treatment process on the first packaging substrate in a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa; and performing a second plasma package-treatment process on the second semiconductor package while performing a second substrate-treatment process on the second packaging substrate and while bonding the first semiconductor package to the first packaging substrate.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Hui-Min Huang, Kai Jun Zhan, Chih-Yuan Chiu, Ming-Da Cheng, Amram Eitan
  • Publication number: 20240404839
    Abstract: A bonded assembly may be formed by: providing a substrate and a semiconductor chip in a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa; disposing the semiconductor chip on the substrate; performing a plasma treatment process on a copper-containing surface of a chip bonding pad on the semiconductor chip in the low-oxygen ambient by directing a plasma jet to the chip bonding pad; and attaching a bonding wire to the semiconductor chip and to the substrate such that a first end of the bonding wire is attached to the copper-containing surface and a second end of the bonding wire is attached to a substrate bonding pad on the substrate.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Hui-Min Huang, Chang-Jung Hsueh, Chih-Yuan Chiu, Jen-Hao Liu, Ming-Da Cheng, Amram Eitan
  • Publication number: 20240404988
    Abstract: A bonded assembly may be formed by providing at least a first packaging substrate in a low-oxygen ambient; providing at least a first semiconductor package in the low-oxygen ambient; performing a first plasma package-treatment process on the first semiconductor package in the low-oxygen ambient by directing at least one first plasma jet to first solder material portions bonded to the first semiconductor package; and bringing the first solder material portions onto, or in proximity to, first substrate-side bonding structures located on the first packaging substrate while the at least one first plasma jet is directed to the first solder material portions. The first substrate-side bonding structures are treated with the first plasma jet. The first semiconductor package is bonded to the first packaging substrate while, or after, the first substrate-side bonding structures are treated with the first plasma jet.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Hui-Min Huang, Kai Jun Zhan, Ming-Da Cheng, Chih-Yuan Chiu, Amram Eitan
  • Publication number: 20240332235
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Inventors: Hui-Min HUANG, Ming-Da CHENG, Wei-Hung LIN, Chang-Jung HSUEH, Kai-Jun ZHAN, Yung-Sheng LIN
  • Publication number: 20240321661
    Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 26, 2024
    Inventors: Chen-Shien Chen, Kuo-Ching Hsu, Wei-Hung Lin, Hui-Min Huang, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20240319551
    Abstract: An electronic device is provided. The electronic device includes a substrate and a first conductive line disposed on the substrate and including a first section and a second section electrically connected to the first section. The first section has a first minimum width outside the overlapping region, the second section has a second minimum width outside the overlapping region, and the first minimum width is different from the second minimum width. The electronic device further includes a first conductive layer disposed on the first section and the second section. The first section is electrically connected to the second section through the first conductive layer.
    Type: Application
    Filed: June 3, 2024
    Publication date: September 26, 2024
    Inventors: Chih-Hao HSU, Chia-Min YEH, Hsieh-Li CHOU, Cheng-Tso CHEN, Hui-Min HUANG, Li-Wei SUNG, Yu-Ti HUANG
  • Publication number: 20240282769
    Abstract: The present disclosure discloses a common source transistor apparatus. The common source transistor unit includes a diffusion area, poly-silicon gates and a source/bulk ring. The diffusion area includes source/bulk areas and drain areas. Each of the poly-silicon gates traverses the diffusion areas between one of the source/bulk areas and one of the drain areas and includes a low-voltage gate part, a first high-voltage gate part and a second high-voltage gate part. The low-voltage gate part includes 2N low-voltage poly-silicon gates. Each of the first and the second high-voltage gate parts is disposed at a side of the low-voltage gate part having one of the source/bulk areas disposed therebetween and includes N+1 high-voltage poly-silicon gates. The source/bulk ring surrounds the diffusion and the poly-silicon gates and is coupled to the source/bulk area. An isolation ring surrounds the common source transistor unit. A substrate ring surrounds the isolation ring.
    Type: Application
    Filed: February 16, 2024
    Publication date: August 22, 2024
    Inventors: HUI-MIN HUANG, CHIEH-PIN CHANG, LI-CHENG CHU, CHUN-CHIEN TSAI, LEAF CHEN
  • Patent number: 12068303
    Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20240258259
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first conductive structure over the semiconductor substrate. The first conductive structure has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive structure. The semiconductor device structure also includes a second conductive structure over the semiconductor substrate. The second conductive structure is substantially as wide as the first conductive structure, and the second conductive structure has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive structure. The first conductive structure is closer to a center point of the semiconductor substrate than the second conductive structure.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 1, 2024
    Inventors: Hui-Min HUANG, Ming-Da CHENG, Wei-Hung LIN, Chang-Jung HSUEH, Kai-Jun ZHAN, Yung-Sheng LIN
  • Publication number: 20240222312
    Abstract: A method for forming a package structure is provided. The method includes transporting a first package component into a processing chamber. The method includes positioning the first package component on a chuck table. The method includes using the chuck table to heat the first package component. The method includes holding a second package component with a bonding head. The bonding head communicates with a plurality of vacuum devices via a plurality of vacuum tubes, and the vacuum devices each operate independently. The method also includes bonding the first package component and the second package component in the processing chamber to form the package structure.
    Type: Application
    Filed: March 12, 2024
    Publication date: July 4, 2024
    Inventors: Kai Jun ZHAN, Chang-Jung HSUEH, Hui-Min HUANG, Wei-Hung LIN, Ming-Da CHENG
  • Patent number: 12025892
    Abstract: An electronic device having a peripheral area is provided. The electronic device includes a substrate; and a first conductive line disposed on the substrate in the peripheral area and including a first section and a second section electrically connected to the first section. An overlapping region is defined as a region that the first section overlaps the second section in a top view of the electronic device. The first section has a first minimum width inside the overlapping region and a second minimum width outside the overlapping region. The second section has a third minimum width outside the overlapping region. The first minimum width is greater than the second minimum width and greater than the third minimum width.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: July 2, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Chih-Hao Hsu, Chia-Min Yeh, Hsieh-Li Chou, Cheng-Tso Chen, Hui-Min Huang, Li-Wei Sung, Yu-Ti Huang
  • Patent number: 12027435
    Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Shien Chen, Kuo-Ching Hsu, Wei-Hung Lin, Hui-Min Huang, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20240215360
    Abstract: A display device includes: a substrate having a display area and a non-display area adjacent to the display area; a first conductive layer disposed on the substrate and including first conductive line; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer and including a second conductive line, wherein, corresponding to the display area, the second conductive line and the first conductive line cross from a top view; a second insulating layer disposed on the second conductive layer; and a third conductive layer disposed on the second insulating layer and including a third conductive line; wherein, corresponding to the non-display area, a portion of a projection of the third conductive line on the substrate is overlapped with a portion of a projection of the first conductive layer on the substrate.
    Type: Application
    Filed: March 7, 2024
    Publication date: June 27, 2024
    Inventors: Hui-Min HUANG, Li-Wei SUNG, Cheng-Tso CHEN, Chia-Min YEH
  • Patent number: 12015002
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface, a protruding connecting portion, and a protruding locking portion, the protruding connecting portion protrudes from the lower surface and passes through the insulating layer and is in direct contact with the first conductive line, the protruding locking portion protrudes from the lower surface and is embedded in the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Min Huang, Ming-Da Cheng, Wei-Hung Lin, Chang-Jung Hsueh, Kai-Jun Zhan, Yung-Sheng Lin
  • Patent number: 12009345
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Patent number: 11990440
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Min Huang, Ming-Da Cheng, Wei-Hung Lin, Chang-Jung Hsueh, Kai-Jun Zhan, Yung-Sheng Lin
  • Publication number: 20240153896
    Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240128148
    Abstract: A method includes attaching a package component to a package substrate, the package component includes: an interposer disposed over the package substrate; a first die disposed along the interposer; and a second die disposed along the interposer, the second die being laterally adjacent the first die; attaching a first thermal interface material to the first die, the first thermal interface material being composed of a first material; attaching a second thermal interface material to the second die, the second thermal interface material being composed of a second material different from the first material; and attaching a lid assembly to the package substrate, the lid assembly being further attached to the first thermal interface material and the second thermal interface material.
    Type: Application
    Filed: January 6, 2023
    Publication date: April 18, 2024
    Inventors: Chang-Jung Hsueh, Po-Yao Lin, Hui-Min Huang, Ming-Da Cheng, Kathy Yan
  • Publication number: 20240128219
    Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.
    Type: Application
    Filed: December 6, 2023
    Publication date: April 18, 2024
    Inventors: Hui-Min Huang, Wei-Hung Lin, Kai Jun Zhan, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng