Patents by Inventor Hui-Min Huang

Hui-Min Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210143534
    Abstract: A method for manufacturing a liquid-crystal antenna device is provided. The method includes step (a) providing a first mother substrate. The first mother substrate includes a first region and a second region. The first region has a plurality of first sides. An extension line of at least one of the first sides divides the second region into a first part and a second part. The method also includes the following steps: (b) forming a first electrode layer on the first region and the second region, and (c) cutting the first mother substrate along the first sides of the first region.
    Type: Application
    Filed: December 18, 2020
    Publication date: May 13, 2021
    Inventors: Yi-Hung LIN, Chin-Lung TING, Hui-Min HUANG, Tang-Chin HUNG
  • Publication number: 20210135092
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate and a dummy MTJ between the first MTJ and the second MTJ, in which a bottom surface of the dummy MTJ is not connected to any metal. Preferably, the semiconductor device further includes a first metal interconnection under the first MTJ, a second metal interconnection under the second MTJ, and a first inter-metal dielectric (IMD) layer around the first metal interconnection and the second metal interconnection and directly under the dummy MTJ.
    Type: Application
    Filed: November 27, 2019
    Publication date: May 6, 2021
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Hung-Yueh Chen, Yu-Ping Wang, Jia-Rong Wu, Rai-Min Huang, Ya-Huei Tsai, I-Fan Chang
  • Publication number: 20210124200
    Abstract: The electronic device includes a first substrate, a second substrate, a first support member, a planarization layer, and an alignment layer. The second substrate is opposite to the first substrate. The first support member is disposed in the peripheral region and located between the first substrate and the second substrate. The planarization layer is disposed on the first substrate and has a first portion and an opening. The first portion is disposed between the opening, and the first support member and the first portion are overlapped in a normal direction of the first substrate. The alignment layer is disposed on the planarization layer. The alignment layer on the first portion has a first thickness. The alignment layer in the opening has a second thickness. The first thickness is greater than or equal to zero and less than the second thickness.
    Type: Application
    Filed: September 26, 2020
    Publication date: April 29, 2021
    Applicant: Innolux Corporation
    Inventors: Shu-Han Yang, Hui-Min Huang, Chia-Min Yeh
  • Patent number: 10985122
    Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10971107
    Abstract: A display device is provided. A first pixel is coupled to a first scan line and a first data line and includes a first light-transmitting area. A second pixel is coupled to a second scan line and a second data line and includes a second light-transmitting area. The size of the second pixel is equal to the size of the first pixel. The area of the second light-transmitting area is different from the area of the first light-transmitting area. A first color area overlaps the first pixel. When first light passes through the first light-transmitting area and the first color area, the first light has a first color. A second color area overlaps the second pixel. When second light passes through the second light-transmitting area and the second color area, the second light has a second color, which is the same as the first color.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: April 6, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Cheng-Tso Chen, Hui-Min Huang, Li-Wei Sung
  • Publication number: 20210091047
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Publication number: 20210055616
    Abstract: An electronic device is provided. The electronic device includes a substrate, a driving circuit disposed on the substrate, an active region disposed on the substrate, and a wiring group disposed on the substrate and between the driving circuit and the active area. The wiring group includes a first conductive line and a second conductive line. The first conductive line has a first section and a second section electrically connected to the first section and disposed between the first section and the active region. The second conductive line includes a third section and a fourth section electrically connected to the third section and disposed between the third section and the active region. The first section and the second section are not the same layer. The first section and the fourth section are the same layer. The second section and the third section are the same layer.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 25, 2021
    Inventors: Chih-Hao HSU, Chia-Min YEH, Hsieh-Li CHOU, Cheng-Tso CHEN, Hui-Min HUANG, Li-Wei SUNG, Yu-Ti HUANG
  • Patent number: 10903559
    Abstract: A method for manufacturing a liquid-crystal antenna device is provided. The method includes step (a) providing a first mother substrate. The first mother substrate includes a first region and a second region. The first region has a plurality of first sides. An extension line of at least one of the first sides divides the second region into a first part and a second part. The method also includes the following steps: (b) forming a first electrode layer on the first region and the second region, and (c) cutting the first mother substrate along the first sides of the first region.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: January 26, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-Hung Lin, Chin-Lung Ting, Hui-Min Huang, Tang-Chin Hung
  • Publication number: 20210013234
    Abstract: An electronic device is provided. The electronic device includes a substrate, a first gate circuit, a second gate circuit, a signal line, and a shielding layer. The substrate includes a display area and a peripheral area. The first gate circuit is disposed in the peripheral area. The second gate circuit is disposed in the peripheral area. The signal line is coupled between the first gate circuit and the second gate circuit. The signal line includes a specific line segment, and the specific line segment overlaps the display area. The shielding layer is disposed in the display area. The shielding layer overlaps the specific line segment.
    Type: Application
    Filed: June 22, 2020
    Publication date: January 14, 2021
    Inventors: Yu-Che CHANG, Li-Wei SUNG, Cheng-Tso CHEN, Hui-Min HUANG, Chia-Min YEH, Hung-Hsun CHEN
  • Publication number: 20200410949
    Abstract: A display device includes a substrate, a plurality of scan lines and a plurality of data lines. The data lines respectively have a first segment that overlaps one of the scan lines and a second segment that is located between adjacent two of the scan lines. A first segment of a first data line and a first segment of a second data line are separated by a distance Wa. A first segment of a third data line and a first segment of a fourth data line are separated by a distance Wc. A second segment of the first data line and a second segment of the second data line are separated by a distance W1. A second segment of the third data line and a second segment of the fourth data line are separated by a distance W3. The distances Wa, Wc, W1 and W3 have a relationship (W1/Wa)?(W3/Wc).
    Type: Application
    Filed: June 14, 2020
    Publication date: December 31, 2020
    Inventors: Chia-Min Yeh, Hui-Min Huang, Hsieh-Li Chou, Cheng-Tso Chen, Yu-Chien Kao, Li-Wei Sung
  • Publication number: 20200395323
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a seed layer over a substrate and forming a first mask layer over the seed layer. The method also includes forming a first trench and a second trench in the first mask layer and forming a first conductive material in the first trench and the second trench. The method further includes forming a second mask layer in the first trench and over the first conductive material, and forming a second conductive material in the second trench and on the first conductive material. A first conductive connector is formed in the first trench with a first height, a second conductive connector is formed in the second trench with a second height, and the second height is greater than the first height.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Inventors: Wen-Hsiung LU, Chang-Jung HSUEH, Chin-Wei KANG, Hui-Min HUANG, Wei-Hung LIN, Cheng-Jen LIN, Ming-Da CHENG, Chien-Chun WANG
  • Patent number: 10861827
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Patent number: 10840111
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protection layer encapsulating the semiconductor die. The chip package also includes a conductive structure in the protection layer and separated from the semiconductor die by the protection layer. The chip package further includes an interconnection structure over the conductive structure and the protection layer. The interconnection structure has a protruding portion between the conductive structure and the semiconductor die, and the protruding portion extends into the protection layer.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shing-Chao Chen, Chih-Wei Lin, Meng-Tse Chen, Hui-Min Huang, Ming-Da Cheng, Kuo-Lung Pan, Wei-Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai
  • Publication number: 20200350197
    Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 5, 2020
    Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10770014
    Abstract: A display device includes a display panel having a display region and a peripheral region. The display panel includes a substrate and a scan driving circuit. The scan driving circuit disposed on the substrate includes a plurality of scan driving blocks and a plurality of first conductive lines. The first conductive lines are respectively coupled to and disposed between adjacent scan driving blocks. The scan driving blocks are disposed corresponding to the peripheral region, and the first conductive lines are disposed corresponding to the display region and the peripheral region.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 8, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Min Yeh, Hung-Hsun Chen, Hui-Min Huang, Cheng-Tso Chen, Li-Wei Sung
  • Publication number: 20200243370
    Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20200144206
    Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.
    Type: Application
    Filed: December 16, 2019
    Publication date: May 7, 2020
    Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10642118
    Abstract: A display substrate is provided. The display substrate includes a first insulating layer disposed on a substrate, a second insulating layer disposed on the first insulating layer. In particular, the first insulating layer has a first opening and the second insulating layer has a second opening, wherein the first opening and the second opening are partially overlapped. Further, in a cross-sectional view, the first insulating layer corresponding to the first opening has two first bottom ends, and the second insulating layer corresponding to the second opening has two second bottom ends, a location of a first vertical central line between the two first bottom ends is different from a location of a second vertical central line between the two second bottom ends, and the first vertical central line and the second vertical central line are substantially parallel to a normal direction of the surface.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 5, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Hung-Kun Chen, Yi-Chin Lee, Hong-Kang Chang, Yu-Chien Kao, Jui-Ching Chu, Li-Wei Sung, Hui-Min Huang
  • Patent number: 10622240
    Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10620656
    Abstract: An operating voltage switching device includes a first current mirror circuit generating a corresponding sensing current according to an input current; a comparator comparing a reference voltage with a voltage at a node of the first current mirror circuit to generate a comparison signal; a first power domain providing a first output current to an internal circuit according to the sensing current; a second power domain providing a second output current to the internal circuit according to the sensing current; and a power domain selecting circuit, which is coupled to the comparator, the first power domain and the second power domain, and selects to enable the first power domain or the second power domain according to the comparison signal; wherein the sensing current is not greater than the input current.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 14, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chih-Cheng Lin, Kai-Yin Liu, Hui-Min Huang