Patents by Inventor Hui-Min Huang
Hui-Min Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230067143Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface, a protruding connecting portion, and a protruding locking portion, the protruding connecting portion protrudes from the lower surface and passes through the insulating layer and is in direct contact with the first conductive line, the protruding locking portion protrudes from the lower surface and is embedded in the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Hui-Min HUANG, Ming-Da CHENG, Wei-Hung LIN, Chang-Jung HSUEH, Kai-Jun ZHAN, Yung-Sheng LIN
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Publication number: 20230065797Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Hui-Min HUANG, Ming-Da CHENG, Chang-Jung HSUEH, Wei-Hung LIN, Kai Jun ZHAN, Wan-Yu CHIANG
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Publication number: 20230062370Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
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Publication number: 20230063127Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Hui-Min HUANG, Ming-Da CHENG, Wei-Hung LIN, Chang-Jung HSUEH, Kai-Jun ZHAN, Yung-Sheng LIN
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Publication number: 20230065724Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate. The semiconductor device structure includes a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate. The semiconductor device structure includes an upper conductive via between the conductive pillar and the interconnection structure. A center of the upper conductive via is laterally separated from a center of the protruding portion by a first distance. The semiconductor device structure includes a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Ming-Da Cheng, Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Po-Hao Tsai, Yung-Sheng Lin
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Patent number: 11567377Abstract: An electronic device is provided. The electronic device includes a substrate, a driving circuit disposed on the substrate, an active area disposed on the substrate, and a wiring group disposed on the substrate and between the driving circuit and the active area. The wiring group includes a first conductive line and a second conductive line. The first conductive line has a first section and a second section electrically connected to the first section and disposed between the first section and the active area. The second conductive line includes a third section and a fourth section electrically connected to the third section and disposed between the third section and the active area. The first section and the second section are not the same layer. The first section and the fourth section are the same layer. The second section and the third section are the same layer.Type: GrantFiled: July 29, 2020Date of Patent: January 31, 2023Assignee: INNOLUX CORPORATIONInventors: Chih-Hao Hsu, Chia-Min Yeh, Hsieh-Li Chou, Cheng-Tso Chen, Hui-Min Huang, Li-Wei Sung, Yu-Ti Huang
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Patent number: 11545465Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.Type: GrantFiled: December 7, 2020Date of Patent: January 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
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Patent number: 11538897Abstract: A display device includes: a substrate having a display area and non-display area; a first conductive layer disposed corresponding to the display area and comprising a first line segment, a second line segment and a third line segment parallel to the first line segment, wherein the first and second line segments are disposed at two sides of the non-display area; a third conductive layer disposed on the substrate and including a first connection line electrically connected to the first and second line segments, and a projection of the first connection line is overlapped with at least a portion of the third line segment; and a first insulating layer disposed between the first and third conductive layers and including a first through-hole and a second through-hole, and the third conductive layer is electrically connected to the first and second line segments via the first and the second through-holes, respectively.Type: GrantFiled: July 20, 2021Date of Patent: December 27, 2022Assignee: INNOLUX CORPORATIONInventors: Hui-Min Huang, Li-Wei Sung, Cheng-Tso Chen, Chia-Min Yeh
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Patent number: 11532498Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.Type: GrantFiled: July 21, 2020Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
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Publication number: 20220384287Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Chen-Shien Chen, Kuo-Ching Hsu, Wei-Hung Lin, Hui-Min Huang, Ming-Da Cheng, Mirng-Ji Lii
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Publication number: 20220278071Abstract: An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.Type: ApplicationFiled: July 8, 2021Publication date: September 1, 2022Inventors: Kai Jun ZHAN, Chang-Jung HSUEH, Hui-Min HUANG, Wei-Hung LIN, Ming-Da CHENG
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Publication number: 20220262694Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.Type: ApplicationFiled: May 12, 2021Publication date: August 18, 2022Inventors: Chen-Shien Chen, Kuo-Ching Hsu, Wei-Hung Lin, Hui-Min Huang, Ming-Da Cheng, Mirng-Ji Lii
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Publication number: 20220252922Abstract: The electronic device includes a first substrate, a second substrate, a first support member, a planarization layer, and an alignment layer. The second substrate is opposite to the first substrate. The first support member is disposed in the peripheral region and located between the first substrate and the second substrate. The planarization layer is disposed on the first substrate and has a first portion and an opening. The first portion is disposed between the opening, and the first support member and the first portion are overlapped in a normal direction of the first substrate. The alignment layer is disposed on the planarization layer. The alignment layer on the first portion has a first thickness. The alignment layer in the opening has a second thickness. The first thickness is greater than or equal to zero and less than the second thickness.Type: ApplicationFiled: April 25, 2022Publication date: August 11, 2022Applicant: Innolux CorporationInventors: Shu-Han Yang, Hui-Min Huang, Chia-Min Yeh
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Patent number: 11387171Abstract: A method of packaging a semiconductor die includes connecting an interposer frame directly to a substrate, wherein the interposer frame has a plurality of conductive columns. The method further includes attaching the semiconductor die to the substrate in an opening of the interposer frame, wherein the semiconductor die directly contacts the substrate. The method further includes forming a molding compound to fill space between the semiconductor die and the interposer frame. The method further includes removing a portion of the molding compound to expose the plurality of conductive columns. The method further includes forming a redistribution layer directly contacting a top surface of the semiconductor die and a top surface of the interposer frame.Type: GrantFiled: June 4, 2018Date of Patent: July 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Min Huang, Shou-Cheng Hu, Chih-Wei Lin, Ming-Da Cheng, Chung-Shi Liu, Chen-Shien Chen
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Patent number: 11347113Abstract: The electronic device includes a first substrate, a second substrate, a first support member, a planarization layer, and an alignment layer. The second substrate is opposite to the first substrate. The first support member is disposed in the peripheral region and located between the first substrate and the second substrate. The planarization layer is disposed on the first substrate and has a first portion and an opening. The first portion is disposed between the opening, and the first support member and the first portion are overlapped in a normal direction of the first substrate. The alignment layer is disposed on the planarization layer. The alignment layer on the first portion has a first thickness. The alignment layer in the opening has a second thickness. The first thickness is greater than or equal to zero and less than the second thickness.Type: GrantFiled: September 26, 2020Date of Patent: May 31, 2022Assignee: Innolux CorporationInventors: Shu-Han Yang, Hui-Min Huang, Chia-Min Yeh
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Patent number: 11289044Abstract: A display device includes a substrate, a plurality of scan lines and a plurality of data lines. The data lines respectively have a first segment that overlaps one of the scan lines and a second segment that is located between adjacent two of the scan lines. A first segment of a first data line and a first segment of a second data line are separated by a distance Wa. A first segment of a third data line and a first segment of a fourth data line are separated by a distance Wc. A second segment of the first data line and a second segment of the second data line are separated by a distance W1. A second segment of the third data line and a second segment of the fourth data line are separated by a distance W3. The distances Wa, Wc, W1 and W3 have a relationship (W1/Wa)?(W3/Wc).Type: GrantFiled: June 14, 2020Date of Patent: March 29, 2022Assignee: InnoLux CorporationInventors: Chia-Min Yeh, Hui-Min Huang, Hsieh-Li Chou, Cheng-Tso Chen, Yu-Chien Kao, Li-Wei Sung
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Patent number: 11239103Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.Type: GrantFiled: April 13, 2020Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
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Publication number: 20210376049Abstract: A display device includes: a substrate having a display area and a non-display area, wherein the non-display area is surrounded by the display area; a first conductive layer disposed on the substrate; a second conductive layer disposed on the substrate, wherein, corresponding to the display area, the second conductive layer and the first conductive layer cross from a top view; a first insulating layer disposed between the first conductive layer and the second conductive layer; a third conductive layer disposed on the substrate and corresponding to the non-display area; and a second insulating layer disposed between the second conductive layer and the third conductive layer, wherein, corresponding to the non-display area, the third conductive layer and the second conductive layer cross from the top view.Type: ApplicationFiled: August 11, 2021Publication date: December 2, 2021Inventors: Hui-Min HUANG, Li-Wei SUNG, Cheng-Tso CHEN, Chia-Min YEH
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Patent number: 11184010Abstract: A receiving end of an electronic device includes an analog front end (AFE) circuit, a phase detector (PD), and a calculation circuit. The AFE circuit receives an input signal and adjusts the phase of the input signal according to a phase control signal. The PD detects the phase of the input signal to generate a current phase value and a phase difference accumulated value, calculates a target phase value according to the phase difference accumulated value, and generates a first phase driving value according to the target phase value and the current phase value. The calculation circuit generates the phase control signal according to the first phase driving value and a phase threshold. After the calculation circuit generates the phase control signal, the phase detector generates a second phase driving value, and the calculation circuit updates the phase threshold according to the first and second phase driving values.Type: GrantFiled: June 23, 2021Date of Patent: November 23, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Yan-Guei Chen, Hsin-Yu Lue, Liang-Wei Huang, Hui-Min Huang
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Patent number: 11177137Abstract: A method includes bonding a first surface of a first semiconductor substrate to a first surface of a second semiconductor substrate and forming a cavity in the first area of the first semiconductor substrate, where forming the cavity comprises: supplying a passivation gas mixture that deposits a passivation layer on a bottom surface and sidewalls of the cavity, where during deposition of the passivation layer, a deposition rate of the passivation layer on the bottom surface of the cavity is the same as a deposition rate of the passivation layer on sidewalls of the cavity; and etching the first area of the first semiconductor substrate using an etching gas, where the etching gas is supplied concurrently with the passivation gas mixture, etching the first area of the first semiconductor substrate comprises etching in a vertical direction at a greater rate than etching in a lateral direction.Type: GrantFiled: January 17, 2020Date of Patent: November 16, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hsiung Lu, Hui-Min Huang, Ming-Da Cheng, Wei-Hung Lin, Chen-En Yen, Hsu-Lun Liu