Abstract: In an HDMI system, the clock regenerator proposed by the HDMI specification may suffer external noise because the input clock of a phase lock loop circuit in a sink device of the HDMI system is too slow. This slow input clock causes the phase lock loop circuit unable to adjust and reduce the jitter of an audio clock regenerated in the sink device. Therefore, one embodiment of the present invention provides a clock regenerator to extract the relationship between the regenerated audio clock and a video clock received by the sink device from other source devices. The clock regenerator may comprise a phase lock loop circuit, a recovery circuit, a crystal oscillator and a tracking circuit. The crystal oscillator generates a crystal clock. The phase lock loop circuit receives the crystal clock and regenerates an audio clock. The recovery circuit extracts the relationship between the audio clock and the received video clock.

Abstract: A standby circuit and method for a display device is disclosed. A detector detects voltage drop of the first termination resistor of a positive path of a clock channel, and the second termination resistors of a negative path. Upon detecting the voltage drop, a switch controller disconnects the positive path or the negative path that has the detected voltage drop, thereby saving power in the standby mode of the display device.

Abstract: The present invention provides a Cinnamomum subavenium extract for inhibiting melanogenesis. The present invention also provides a composition for inhibiting melanogenesis including compounds inhibit tyrosinase activity.

Abstract: A method for adjusting a serial data signal having multiple sets of bits includes the following steps. First, one set of bits in the serial data signal is over-sampled to generate a first set of over-sampled bits. Next, every adjacent two bits of the first set of over-sampled bits are compared to generate one set of edge bits. Then, a delay operation is determined according to the set of edge bits. Afterwards, a displacement operation is executed on next sets of bits in the serial data signal according to the delay operation.

Abstract: A voltage regulator and an integrated circuit using the voltage regulator is provided. The voltage regulator has a bandgap reference circuit, an operational amplifier, a power transistor and a voltage divider. The bandgap reference circuit generates a bandgap reference voltage. The operational amplifier receives the bandgap reference voltage and a feedback voltage to output a control signal for the power transistor. The power transistor is powered by a first voltage source and transforms the first voltage source to a second voltage source according to the control signal. The second voltage source is divided by the voltage divider to generate the feedback voltage and is further used in powering the bandgap reference circuit and the operational amplifier.

Abstract: A data transmission system includes a transmitter and a receiver. The transmitter mixes an original clock signal and an original data signal to generate and output a hybrid differential signal, the hybrid differential signal having multiple clock pulses and multiple data pulses. At lease one data pulse occurs between two clock pulses, and the period between two clock pulses corresponds to the frequency of the original clock signal. The clock pulses and the data pulses have different differential swings. The receiver receives the hybrid differential signal via a bus and generates a recovered clock signal and a recovered data signal based on the hybrid differential signal. The hybrid differential signal, the original clock signal and the original data signal are reduced swing differential signals.

Abstract: A fully foldable storage box includes a soft bottom, and four hard side boards perpendicularly coupled to four edges of the bottom, and edges of the side boards are connected with each other to constitute a structure having a first folding line along each of four edge corners of the storage box, and a second folding line is disposed perpendicularly at the middle of two selected corresponding lateral boards and a third folding line is disposed perpendicularly at a side of the two lateral boards and proximate to the rear board, such that support strips are formed between the two lateral boards and the rear board respectively, and a liftable hard bottom board is coupled to an internal bottom edge of the rear board, so that and the bottom board can be stacked onto the soft bottom to constitute a fully foldable storage box.

Abstract: A high frequency SAW device and the substrate thereof are disclosed. The disclosed high frequency SAW device does not need to use the conventional and expensive sapphire substrate as its substrate. Besides, the disclosed substrate for a high-frequency SAW device can replace the conventional sapphire substrate in the use of the substrate for a high frequency SAW device. The disclosed high frequency SAW device comprises: a substrate; a first buffering layer forming on the surface of the substrate; a second buffering layer forming on the surface of the first buffering layer; a piezoelectric layer forming on the surface of the second buffering layer; an input transformation unit; and an output transformation unit, wherein the input transformation unit and the output transformation unit are formed in pairs on the surface of or beneath the piezoelectric layer.

Abstract: A source driving circuit includes a gamma voltage generator, a common voltage generator and a driver. The gamma voltage generator receives gamma data from a timing controller through reduced swing differential signaling (RSDS) transmission interface to generate corresponding gamma voltages. The common voltage generator receives common voltage data from the timing controller to generate a corresponding common voltage. The driver receives image data from the timing controller through the RSDS transmission interface, the gamma voltages from the gamma voltage generator and the common voltage from the common voltage generator for modifying the image data using the gamma voltages and the common voltage and transmitting the modified image data to a panel of the liquid crystal display.

Abstract: A standby circuit and method for a display device is disclosed. A detector detects voltage drop of the first termination resistor of a positive path of a clock channel, and the second termination resistors of a negative path. Upon detecting the voltage drop, a switch controller disconnects the positive path or the negative path that has the detected voltage drop, thereby saving power in the standby mode of the display device.

Abstract: A high frequency SAW device and the substrate thereof are disclosed. The disclosed high frequency SAW device does not need to use the conventional and expensive sapphire substrate as its substrate. Besides, the disclosed substrate for a high-frequency SAW device can replace the conventional sapphire substrate in the use of the substrate for a high frequency SAW device. The disclosed high frequency SAW device comprises: a substrate; a first buffering layer forming on the surface of the substrate; a second buffering layer forming on the surface of the first buffering layer; a piezoelectric layer forming on the surface of the second buffering layer; an input transformation unit; and an output transformation unit, wherein the input transformation unit and the output transformation unit are formed in pairs on the surface of or beneath the piezoelectric layer.

Abstract: It is difficult to implement a conventional phase lock loop circuit in a sink device within an HDMI system because the low frequency input causes the conventional phase lock loop circuit to absorb unnecessary noise during a long waiting period. Therefore, the present invention provides a low jitter clock regenerator comprises: an input clock; a divider to divide said input clock into a slower clock; a phase lock loop circuit to regenerate said slower clock to a reference clock; and a parameter transformer to tune said divider and said phase lock loop circuit to increase the adjustment speed of said phase lock loop circuit. The present invention also provides a method to reorganize parameters in order to create new parameters which are better suitable for a clock recovery circuit in a sink device within an HDMI system.

Abstract: A data transmission system includes a transmitter and a receiver. The transmitter mixes an original clock signal and an original data signal to generate and output a hybrid differential signal, the hybrid differential signal having multiple clock pulses and multiple data pulses. At lease one data pulse occurs between two clock pulses, and the period between two clock pulses corresponds to the frequency of the original clock signal. The clock pulses and the data pulses have different differential swings. The receiver receives the hybrid differential signal via a bus and generates a recovered clock signal and a recovered data signal based on the hybrid differential signal. The hybrid differential signal, the original clock signal and the original data signal are reduced swing differential signals.

Abstract: A method for adjusting a serial data signal having multiple sets of bits includes the following steps. First, one set of bits in the serial data signal is over-sampled to generate a first set of over-sampled bits. Next, every adjacent two bits of the first set of over-sampled bits are compared to generate one set of edge bits. Then, a delay operation is determined according to the set of edge bits. Afterwards, a displacement operation is executed on next sets of bits in the serial data signal according to the delay operation.

Abstract: This invention features a kit containing multiple expression vectors for producing tag-cleavable fusion proteins in various expression systems, or for producing fusion proteins in E. coli inclusion bodies.

Abstract: A digital-to-analog converter outputting an output analog voltage according to an N-bit digital signal is provided. The digital-to-analog converter includes a first and a second resistor strings, a first and a second select units. The first resistor string is connected between a first and a second power supply voltages to generate a first group of reference voltages. The first select unit selects two reference voltages out of the first group according to M most significant bits of the N-bit digital signal. The second resistor string is connected between the selected reference voltages to generate a second group of reference voltages between the selected reference voltages. The second select unit selects one reference voltage out of the second group as the output analog voltage according to the N-M least significant bits of the N-bit digital signal.

Abstract: In an HDMI system, the clock regenerator proposed by the HDMI specification may suffer external noise because the input clock of a phase lock loop circuit in a sink device of the HDMI system is too slow. This slow input clock causes the phase lock loop circuit unable to adjust and reduce the jitter of an audio clock regenerated in the sink device. Therefore, one embodiment of the present invention provides a clock regenerator to extract the relationship between the regenerated audio clock and a video clock received by the sink device from other source devices. The clock regenerator may comprise a phase lock loop circuit, a recovery circuit, a crystal oscillator and a tracking circuit. The crystal oscillator generates a crystal clock. The phase lock loop circuit receives the crystal clock and regenerates an audio clock. The recovery circuit extracts the relationship between the audio clock and the received video clock.

Abstract: A multi-channel receiver, digital edge tuning circuit and a method for operating the same is disclosed. The digital edge tuning circuit for tuning phases of an input signal and a clock signal, comprises a delay-tuning circuit for receiving the input signal and delaying the input signal to generate a fine-tuned signal; a delay set comprising a plurality of delays connected serially one by one, the input of the delay set coupled to the fine-tune circuit, for receiving the fine-tuned signal; a plurality of sample/hold circuits, each of the sample/hold circuits coupled to a corresponding output of one of the delays and the fine-tune circuit, for sampling and holding the corresponding output; and a dynamic edge tuning circuit, coupled to the sample/hold circuits, for controlling a common delay time delayed by the delay-tuning circuit according to which one of the sample/hold circuits samples a data edge of the input signal.

Abstract: A reference voltage generator is provided. The reference voltage generator includes a bandgap reference circuit, a level shifter and a voltage divider. The bandgap reference circuit includes a current generator and a first BJT. The current generator outputs a reference current. The first BJT flows in the reference current from its emitter via a first resistor and has its collector and base grounded, such that a bandgap reference voltage and a first bias voltage can be output at the connection between the current generator and the first resistor and at the emitter of the first BJT. The level shifter is coupled to the bandgap reference circuit and outputs a second bias voltage higher than the first bias voltage and unequal to the bandgap reference voltage. The voltage divider is connected between the second bias voltage and the bandgap reference voltage and outputs a reference voltage therebetween.

Abstract: A data communication system comprises a transmitter and a receiver. A plurality of current mode drivers at the transmitter are used to transmit clock and data signals to the receiver. A plurality of current mode sinks at the receiver are used to receive the transmitted clock and data signal. The present invention provides an improved current mode interface receiver with a process insensitive common mode current extraction circuit. The proposed common mode current extraction circuit will generate a current reference based on the received clock signal, so as to accurately interpret the received clock and data signals.