Abstract: The present invention provides an IPS TFT array substrate and a manufacturing method thereof. The manufacturing method of an IPS TFT array substrate of the present invention includes: forming a gate electrode, a scan line, a pixel electrode, and a common electrode with a first mask-involved operation, forming a first through hole and a second through hole in the gate insulation layer and an active layer with a second mask-involved operation, and forming a source electrode, a drain electrode, a data line, and a common electrode line with a third mask-involved operation. The present invention uses only three mask-involved operations to complete the manufacturing of an IPS TFT array substrate. Compared to the state of the art, the number of masks used is reduced, the manufacturing time is shortened, and thus the manufacturing cost is lowered. The IPS TFT array substrate of the present invention has a simple manufacturing process, a low manufacturing cost, and excellent electrical properties.

Abstract: An array substrate, a manufacturing method and a display panel thereof are provided. A single mask process is used for completing formation of a flat layer and a pixel definition layer, or the flat layer, the pixel definition layer and a spacer. A light emitting unit is located within an anode so that the light of the emitting unit is reflected by the anode to accumulate. The risk of color mixing on the display panel is reduced, and the light intensity on the light exit side is enhanced.

Abstract: An array substrate, a manufacturing method thereof, and a display panel are provided in the present application. A gate electrode and source and drain electrodes of different thickness are formed on an electroplated substrate by metal electroplating. By using a height difference between the gate electrode and the source and drain electrodes, a dielectric layer covering the gate electrode and exposing the source and drain electrodes is formed on a substrate, so that an active layer is electrically connected to the source and drain electrodes. Moreover, separation is realized by means of the dielectric layer and the gate electrode, so an etching stop layer is not needed, which simplifies an IGZO manufacturing process and reduces production costs.

Abstract: The present invention relates to a scalable process for the making of elagolix, its salts and the process of intermediate compounds.

Abstract: A thin-film transistor and a manufacturing method for the same are disclosed.

Abstract: The present invention teaches a TFT array substrate and its manufacturing method including the following steps. A data line and a ring-shaped source electrode are formed on a substrate. A first insulation layer is formed on the substrate. A ring trough exposing the source electrode is formed on the first insulation layer. A semiconductor active layer is formed in the ring trough. A channel is formed on the first insulation layer in an area surrounded by the ring trough. A gate line, a gate electrode in the channel, and a drain electrode connected to the semiconductor active layer are formed on the first insulation layer. A second insulation layer is formed on the first insulation layer, and a pixel via is formed on the second insulation layer. A pixel electrode is formed on the second insulation layer, and is connected to the drain electrode through the pixel via.

Abstract: The present invention teaches a pixel unit including thin film transistors (TFTs) and pixel electrodes corresponding to the TFTs. The pixel electrodes are connected to the source electrodes of the TFTs. Each pixel electrode includes multiple arc-shaped electrode units arranged at intervals along an axial direction around a periphery of a corresponding TFT. The electrode units are electrically connected together. The present invention adopts arc-shaped pixels (similar to concentric circles) so that liquid crystal molecules are closer to being isotropic. Then, by having different vertical alignment (VA) TFT designs in the primary pixel region and secondary pixel region and utilizing the differences in W/L and capacitance, different voltage levels for primary pixel electrode and secondary pixel electrode are achieved. The color shift problem is improved and the viewing angle is enhanced.

Abstract: The present invention teaches a TFT array substrate and its manufacturing method including the following steps. A data line and a ring-shaped source electrode are formed on a substrate. A first insulation layer is formed on the substrate. A ring trough exposing the source electrode is formed on the first insulation layer. A semiconductor active layer is formed in the ring trough. A channel is formed on the first insulation layer in an area surrounded by the ring trough. A gate line, a gate electrode in the channel, and a drain electrode connected to the semiconductor active layer are formed on the first insulation layer. A second insulation layer is formed on the first insulation layer, and a pixel via is formed on the second insulation layer. A pixel electrode is formed on the second insulation layer, and is connected to the drain electrode through the pixel via.

Abstract: A thin-film transistor and a manufacturing method for the same are disclosed.

Abstract: An array substrate and a method of manufacturing the same are provided. The array substrate includes a substrate, a gate layer, a first insulating layer, a gate tracking layer, and a second insulating layer. The method of manufacturing the array substrate includes a substrate providing step, a gate layer forming step, a first insulating layer forming step, a gate tracking layer forming step, and a second insulating layer forming step.

Abstract: The present disclosure proposes a thin film transistor and a related circuit. The thin film includes a gate, a drain and a source. The gate includes one or more gate units. The gate unit includes two or more strip-shaped gate branches, and a first gap is arranged between the two adjacent strip-shaped gate branches to separate them.

Abstract: The present disclosure provides a positive electrode of lithium-ion battery, an all-solid-state lithium-ion battery and a preparation method thereof, and an electrical device. The all-solid-state lithium-ion battery of the present disclosure includes a positive electrode, a solid electrolyte, and a negative electrode; wherein the positive electrode includes a positive electrode current collector and a positive electrode material layer provided on a surface of the positive electrode current collector, a positive electrode active material in the positive electrode material layer is a manganese oxygen compound; and the negative electrode includes a negative electrode current collector and a negative electrode material layer provided on a surface of the negative electrode current collector, a negative electrode active material in the negative electrode material layer is a titanium oxygen compound.

Abstract: The present invention provides a VA type TFT array substrate and a manufacturing thereof. The manufacturing method for a VA type TFT array substrate of the present invention comprises that three pixel electrodes are formed in one pixel. The three pixel electrodes are connected to the same TFT but located on different structure layers. Therefore, the driving capabilities to liquid crystals are different. In the present invention, the three pixel electrodes are used to adjust the liquid crystal transmittances of three regions in one pixel, which is beneficial of keeping the brightness uniformity of the pixel when seeing from different angels, thereby enhancing the viewing angle of the VA type LCDs. The VA type TFT array substrate of the present invention disposes three pixel electrodes are formed in one pixel, which is beneficial of enhancing the viewing angle of the VA type LCDs.

Abstract: The present invention provides a VA type TFT array substrate and a manufacturing thereof. The manufacturing method for a VA type TFT array substrate of the present invention comprises that three pixel electrodes are formed in one pixel. The three pixel electrodes are connected to the same TFT but located on different structure layers. Therefore, the driving capabilities to liquid crystals are different. In the present invention, the three pixel electrodes are used to adjust the liquid crystal transmittances of three regions in one pixel, which is beneficial of keeping the brightness uniformity of the pixel when seeing from different angels, thereby enhancing the viewing angle of the VA type LCDs. The VA type TFT array substrate of the present invention disposes three pixel electrodes are formed in one pixel, which is beneficial of enhancing the viewing angle of the VA type LCDs.

Abstract: A method of manufacturing an array substrate is provided. The method divides an array substrate into a curing area and a stretchable area. A metal wiring corresponding to the stretchable area is made of a flexible conductive material, so as to reduce disconnection risk of the display panel during bending.

Abstract: The disclosure provides a manufacturing method for a thin film transistor, wherein a manufacturing method for a data line and a source/drain specifically includes: S21: respectively manufacturing a data line material film layer and a source/drain material film layer; S22: manufacturing a photoresist material film layer; S23: performing a half-tone method to etch the photoresist material film layer, forming a photoresist layer, and obtaining a first etching substrate; S24: performing a 4-mask process to etch the first substrate, forming the data line on a gate insulating layer, forming the source and the drain on an active layer, and forming a the back channel between the source and the drain to obtain the thin film transistor. The disclosure further provides a manufacturing method for an array substrate, wherein the manufacturing method for an array substrate includes the above-mentioned manufacturing method for a thin film transistor.

Abstract: The present disclosure discloses a manufacturing method of a thin film transistor, including: forming a gate layer on a substrate; forming a gate insulating layer on the gate layer and the substrate; forming an active layer on the gate insulating layer; and simultaneously forming a source and a drain formed on the active layer by a combination of a chemical plating method and a lift-off method. In the present disclosure, the chemical plating method is combined with the lift-off method, so that the wet-etching method is not used for forming the source and the drain, and thus the IGZO at the channel is not required to be protected by the etching-stop-layer. Therefore, while simplifying the production process, but also can reduce costs.

Abstract: The present application discloses an array substrate and a method of manufacturing the same. The array substrate includes a first insulating layer disposed on the substrate; a source electrode pattern disposed within the first insulating layer; an annular gate electrode pattern disposed on the first insulating layer and surrounded the periphery of the source electrode pattern; a second insulating layer covering on the annular gate electrode pattern; a semiconductor pattern disposed in the annular area of the annular gate electrode pattern, and is electrically connected to the exposed portion of the source electrode pattern, the semiconductor pattern is further electrical insulation to the annular gate electrode pattern through the second insulating layer; a pixel electrode disposed on the second insulating layer and electrically connected to a side of the semiconductor pattern remote from the substrate.

Abstract: An array substrate includes a pixel structure formed on a substrate. The pixel structure is provided with a transistor region and a pixel region. A source electrode and a drain electrode in the pixel region are located in the transistor region and insulated from each other. A data line is electrically connected to the drain electrode. A pixel electrode is located in the pixel region and electrically connected to the source electrode. A copper metal layer is deposited on the data line and a drain electrode; a semiconductor active layer is formed between the source and drain electrodes and respectively connecting with the source and drain electrodes; a gate insulating layer overlying the data line and the drain electrode. The transparent electrode layer, the copper metal layer and the semiconductor active layer; the gate line and the gate electrode electrically connect to each other on the gate insulating layer.

Abstract: A thin film transistor is provided, including a base substrate, a semiconductor active layer, a gate electrode, a gate insulating layer, a source electrode and a drain electrode. The gate insulating layer is formed on the base substrate, the gate insulating layer is provided with a through hole and an annular groove surrounding the through hole. The gate electrode is formed in the through hole, the semiconductor active layer is formed in the annular groove, a height of the gate electrode in the through hole is at least higher than a bottom of the annular groove. The source electrode and the drain electrode are formed on the gate insulating layer at intervals and connected to the semiconductor active layer, respectively. A method of manufacturing the thin film transistor and an array substrate including the thin film transistor are also provided.