Patents by Inventor Hui-Yu Chen

Hui-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152246
    Abstract: A joystick includes a stick head, an actuating component, a substrate, a bearing base, a resilient recovering component, a first rotation component and a second rotation component. The actuating component has a first end and a second end opposite to each other. The first end is connected to the stick head, and an identification feature is disposed on the second end. The substrate has a detector used to detect the identification feature and determine motion of the stick head. The bearing base is disposed on the substrate. The resilient recovering component is disposed between the substrate and the bearing base. The first rotation component is movably disposed on the bearing base and rotatable in a first direction. The second rotation component is movably connected to the first rotation component and rotatable in a second direction different from the first direction, and connected to the actuating component in a rotatable manner.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Applicant: PixArt Imaging Inc.
    Inventors: Hung-Yu Lai, Yong-Nong Huang, Hui-Hsuan Chen, Jia-Hong Huang
  • Publication number: 20240145559
    Abstract: A transistor structure includes a substrate, a source electrode, a drain electrode, a protective layer and a gate electrode. The source electrode and the drain electrode are provided on the substrate. The protective layer is provided on the substrate. The protective layer is provided between the source electrode and the drain electrode. The protective layer includes a SiNx layer and a SiOx layer. The SiOx layer is provided on the substrate, the SiNx layer is provided on the SiOx layer, and a through hole of the protective layer is formed to extend through the SiNx layer and the SiOx layer. The gate electrode is provided in the through hole, and the gate electrode is separated from at least part of the SiOx layer so as to form an air gap therebetween.
    Type: Application
    Filed: December 21, 2022
    Publication date: May 2, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang-Yan HSIEH, Po-Tsung TU, Jui-Chin CHEN, Hui-Yu CHEN, Po-Chun YEH
  • Publication number: 20240141123
    Abstract: A manufacturing method of a modified polymer layer modified by hydroxyapatite is provided in the present disclosure, including following steps: (a) providing a polymer layer; (b) plasma-activating acrylic acid using an atmospheric cold plasma device to modify a surface of the polymer layer to obtain an acrylic-modified polymer layer; (c) immersing the acrylic-modified polymer layer in a first solution containing a calcium ion to obtain a calcium-containing modified layer; and (d) immersing the calcium-containing modified layer in a second solution containing phosphate salt to obtain a modified polymer layer modified by hydroxyapatite.
    Type: Application
    Filed: June 9, 2023
    Publication date: May 2, 2024
    Inventors: Wei-Yu CHEN, Jui-Sheng LEE, Hui-Ju HSU
  • Patent number: 11963969
    Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: April 23, 2024
    Assignee: BUDDHIST TZU CHI MEDICAL FOUNDATION
    Inventors: Chia-Yu Chang, Shinn-Zong Lin, Hsiao-Chien Ting, Hui-I Yang, Horng-Jyh Harn, Hong-Lin Su, Ching-Ann Liu, Yu-Shuan Chen, Tzyy-Wen Chiou, Tsung-Jung Ho
  • Patent number: 11964358
    Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yu Wang, Chun-Hao Kung, Ching-Hsiang Tsai, Kei-Wei Chen, Hui-Chi Huang
  • Publication number: 20240130246
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.
    Type: Application
    Filed: December 25, 2023
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Patent number: 11957061
    Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Yi-Yu Lin, Ching-Hua Hsu, Hung-Yueh Chen
  • Patent number: 11942563
    Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: March 26, 2024
    Assignee: XINTEC INC.
    Inventors: Chia-Sheng Lin, Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen
  • Publication number: 20240096756
    Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
  • Patent number: 11934626
    Abstract: A joystick includes a stick head, an actuating component, a substrate, a bearing base, a resilient recovering component and a constraining component. The actuating component has a first end and a second end opposite to each other. The first end is connected to the stick head, and an identification feature is disposed on the second end. The substrate has a detection module used to detect the identification feature and determine motion of the stick head. The bearing base is disposed on the substrate. An opening portion of the bearing base aligns with the detection module and the actuating component. The resilient recovering component is disposed between the substrate and the bearing base. The constraining component is disposed on the resilient recovering component and movably disposed inside the opening portion, and used to abut against the actuating component in a detachable manner.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: March 19, 2024
    Assignee: PixArt Imaging Inc.
    Inventors: Hung-Yu Lai, Yong-Nong Huang, Hui-Hsuan Chen, Jia-Hong Huang
  • Publication number: 20240086611
    Abstract: Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Hsuan Chiu, Chih-Liang Chen, Hui-Zhong Zhuang, Chi-Yu Lu, Kuang-Ching Chang
  • Publication number: 20240088126
    Abstract: A method includes creating a layout design of the integrated circuit after determining a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor. Creating the layout design includes forming first-type active zone patterns, forming second-type active zone patterns, generating a gate-strip pattern, and positioning the gate-strip pattern over the first-type active zone patterns and the second-type active zone patterns. Creating the layout design also includes determining whether to generate one or more poly cut patterns that intersect the gate-strip, based on the difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Jian-Sing LI, Chi-Yu LU, Hui-Zhong ZHUANG, Chih-Liang CHEN
  • Patent number: 11925035
    Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: March 5, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kai Hsu, Hui-Lin Wang, Ching-Hua Hsu, Yi-Yu Lin, Ju-Chun Fan, Hung-Yueh Chen
  • Patent number: 11778134
    Abstract: The present invention relates to a fault detection circuit for detecting one or more column faults in a pixel array of an image sensor. The present invention further relates to a readout circuit for reading out a column line of an image sensor, and to an image sensor comprising the same. The fault detection circuit according to the invention comprises a signal unit for applying an electrical signal to a given column line of the pixel array, a determining unit for measuring a response to the applied electrical signal and for determining whether a fault exists for said given column line in dependence of the measured response, and a controller for controlling the signal unit and the determining unit, and for outputting a fault status for said given column line.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: October 3, 2023
    Assignee: TELEDYNE DALSA B.V.
    Inventors: Willem J. Kindt, Hui-Yu Chen
  • Publication number: 20210352224
    Abstract: The present invention relates to a fault detection circuit for detecting one or more column faults in a pixel array of an image sensor. The present invention further relates to a readout circuit for reading out a column line of an image sensor, and to an image sensor comprising the same. The fault detection circuit according to the invention comprises a signal unit for applying an electrical signal to a given column line of the pixel array, a determining unit for measuring a response to the applied electrical signal and for determining whether a fault exists for said given column line in dependence of the measured response, and a controller for controlling the signal unit and the determining unit, and for outputting a fault status for said given column line.
    Type: Application
    Filed: February 24, 2021
    Publication date: November 11, 2021
    Inventors: Willem J. Kindt, Hui-Yu Chen
  • Publication number: 20180374566
    Abstract: A system for monitoring administered liquid substance includes a medicine administration system including an employee bar coded label, a patient bar coded label, a medicine bar coded label, and a medicine controller having a medicine controller bar coded label and a medicine administration device; and an administration monitoring system including a computer for medication, a barcode reader, and a handheld mobile device. The barcode reader scans the employee bar coded label, the patient bar coded label, the medicine bar coded label, and the medicine controller bar coded label and sends the read barcodes to the computer for medication; a volume of substance to be administered is set by the medicine controller based on the read barcodes; the medicine controller outputs the set volume of substance to the computer for medication; the computer for medication compares the set volume of substance with a volume of substance written on the EMR, and a comparison result is sent to the handheld mobile device for showing.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 27, 2018
    Inventors: CHIH-WEI CHEN, HUI-YU CHEN
  • Patent number: 9228196
    Abstract: The present invention provides a method for changing nitrogen utilization efficiency in a plant comprises regulating the expression of Arabidopsis NRT 1.7 or an ortholog thereof so that the nitrate remobilization from older leaves to young leaves in the plant is regulated, thereby the nitrogen utilization efficiency is changed. The present invention also provides a transgenic plant obtainable by transforming a plant with an expression construct with a high or low level of expression of NRT 1.7. On the other hand, the present invention yet provides a chimera nitrate transporter, a DNA molecule coding for this chimera transporter and an expression vector thereof.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: January 5, 2016
    Assignee: Academia Sinica
    Inventors: Yi-Fang Tsay, Shu-Chun Fan, Hui-Yu Chen, Kuo-En Chen
  • Publication number: 20140201863
    Abstract: The present invention provides a method for changing nitrogen utilization efficiency in a plant comprises regulating the expression of Arabidopsis NRT 1.7 or an orthologue thereof so that the nitrate remobilization from older leaves to young leaves in the plant is regulated, thereby the nitrogen utilization efficiency is changed. The present invention also provides a transgenic plant obtainable by transforming a plant with an expression construct with a high or low level of expression of NRT 1.7. On the other hand, the present invention yet provides a chimera nitrate transporter, a DNA molecule coding for this chimera transporter and an expression vector thereof.
    Type: Application
    Filed: October 30, 2013
    Publication date: July 17, 2014
    Applicant: Academia Sinica
    Inventors: Yi-Fang Tsay, Shu-Chun Fan, Hui-Yu Chen
  • Patent number: 8414794
    Abstract: A blue phase liquid crystal composition includes a chiral dopant, a positive liquid crystal component and a negative liquid crystal component. The positive liquid crystal component includes at least one positive liquid crystal material, has a positive dielectric anisotropy and has no blue phase properties with respect to the chiral dopant. In addition, the negative liquid crystal component includes at least one negative liquid crystal material, has a negative dielectric anisotropy and has no blue phase properties with respect to the chiral dopant, so that the blue phase liquid crystal composition has a dielectric anisotropy between 0.5 and 14 and a blue phase temperature range larger than 3° C.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: April 9, 2013
    Assignees: Feng Chia University, Chunghwa Picture Tubes, Ltd.
    Inventors: Hsin-Hung Liu, Hui-Yu Chen, Ji-Yi Chou, Jia-Liang Lai, Yu-Hsien Chen, Huai-An Li
  • Publication number: 20120273721
    Abstract: A blue phase liquid crystal composition includes a chiral dopant, a positive liquid crystal component and a negative liquid crystal component. The positive liquid crystal component includes at least one positive liquid crystal material, has a positive dielectric anisotropy and has no blue phase properties with respect to the chiral dopant. In addition, the negative liquid crystal component includes at least one negative liquid crystal material, has a negative dielectric anisotropy and has no blue phase properties with respect to the chiral dopant, so that the blue phase liquid crystal composition has a dielectric anisotropy between 0.5 and 14 and a blue phase temperature range larger than 3° C.
    Type: Application
    Filed: November 3, 2011
    Publication date: November 1, 2012
    Inventors: Hsin-Hung Liu, Hui-Yu Chen, Ji-Yi Chou, Jia-Liang Lai, Yu-Hsien Chen, Huai-An Li