Patents by Inventor Hui Zhong

Hui Zhong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955774
    Abstract: Provided is an elliptical multi-mesa laser structure, including a substrate layer, an N-DBR, a functional layer and a P-DBR sequentially arranged from bottom to top. The substrate layer is fixedly connected with an N contact layer. The N-DBR is fixedly connected to a top of the substrate layer, and the N contact layer is arranged around the N-DBR. A space layer is inserted in the N-DBR. The functional layer is fixedly connected to a top of the N-DBR. The P-DBR is fixedly connected to a top of the functional layer, and a top of the P-DBR is fixedly connected with a P contact layer. Another space layer is inserted into the P-DBR.
    Type: Grant
    Filed: July 1, 2023
    Date of Patent: April 9, 2024
    Assignee: SHENZHEN TECHNOLOGY UNIVERSITY
    Inventors: Hui Li, Jian Feng, Chuyu Zhong, Wei Miao, Shilong Zhao, Zhao Chen
  • Patent number: 11948886
    Abstract: A semiconductor device includes one or more active semiconductor components, wherein a front side is defined over the semiconductor substrate and a back side is defined beneath the semiconductor substrate. A front side power rail is formed at the front side of the semiconductor device and is configured to receive a first reference power voltage. First and second back side power rails are formed on the back side of the semiconductor substrate and are configured to receive corresponding second and third reference power voltages. The first, second and third reference power voltages are different from each other.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Publication number: 20240105555
    Abstract: A semiconductor device includes first and second gate structures, a metallization layer, and first and second tie-off contacts. The first and second gate structures extend substantially along a first direction and are aligned with each other substantially along the first direction. The metallization layer includes a Vdd line, a Vss line, metal lines between the Vdd line and the Vss line and extending substantially along a second direction different from the first direction. The first tie-off contact overlaps an intersection of the first gate structure and a first one of the Vdd line and the Vss line from a top view. The second tie-off contact overlaps an intersection of the second gate structure and a first one of the metal lines from the top view, wherein said first one of the metal lines is adjacent to a second one of the Vdd line and the Vss line.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Satyabrata DASH, Jian-Sing LI, Hui-Zhong ZHUANG
  • Publication number: 20240105726
    Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 28, 2024
    Inventors: Shao-Lun Chien, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue
  • Publication number: 20240104288
    Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Inventors: Shih-Wei PENG, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Shun Li CHEN, Wei-Cheng LIN
  • Patent number: 11942420
    Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
  • Publication number: 20240096756
    Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
  • Publication number: 20240096865
    Abstract: A semiconductor device, includes a first metal layer, a second metal layer, a drain/source contact and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The drain/source contact extends in the second direction and is connected to the second conductor. The at least one conductive via connects the first conductor and the second conductor through the third conductor.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Wei-Hsin TSAI, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
  • Patent number: 11935888
    Abstract: A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pin-Dai Sue, Ting-Wei Chiang, Hui-Zhong Zhuang, Ya-Chi Chou, Chi-Yu Lu
  • Publication number: 20240088126
    Abstract: A method includes creating a layout design of the integrated circuit after determining a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor. Creating the layout design includes forming first-type active zone patterns, forming second-type active zone patterns, generating a gate-strip pattern, and positioning the gate-strip pattern over the first-type active zone patterns and the second-type active zone patterns. Creating the layout design also includes determining whether to generate one or more poly cut patterns that intersect the gate-strip, based on the difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Jian-Sing LI, Chi-Yu LU, Hui-Zhong ZHUANG, Chih-Liang CHEN
  • Publication number: 20240086611
    Abstract: Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Hsuan Chiu, Chih-Liang Chen, Hui-Zhong Zhuang, Chi-Yu Lu, Kuang-Ching Chang
  • Patent number: 11928513
    Abstract: Mechanisms are provided for scheduling a workload in a cloud computing system. A cloud affinity factor (CAF) computer model is trained, via a machine learning process based on a training dataset comprising static characteristics of a workload binary for a workload, and dynamic characteristics corresponding to historical performance data for the workload, such that the trained CAF computer model predicts a performance classification for a given workload binary. The trained CAF computer model processes a new workload to generate a performance classification for the new workload. Cloud affinity factor(s) are generated based on the performance classification for the new workload. Node affinity and dispatch rule(s) are applied to the cloud affinity factor(s) to select one or more nodes of the cloud computing system to which to dispatch the workload. The workload is then scheduled on the selected one or more nodes.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Peng Hui Jiang, Dong Hui Liu, Jia Tian Zhong, Xing Xing Shen, Jia Yu, Yong Yin
  • Patent number: 11918980
    Abstract: A catalyst for continuous production of 1,1,1,3-tetrachloropropane through gas-solid reaction as well as a preparation method and use thereof are provided. The catalyst includes a zero-valent iron and phosphorus co-modified carbon material which includes a carbon material as a carrier, a zero-valent iron supported onto the carrier and serving as an active component, and a phosphate functional group formed on the surface of the carbon material. The preparation method includes: co-modifying a carbon material using a ferric salt and organic phosphorus to obtain the catalyst for continuous production of 1,1,1,3-tetrachloropropane through gas-solid reaction. The present application further provides a method for continuous production of 1,1,1,3-tetrachloropropane through gas-solid reaction.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: March 5, 2024
    Assignees: NINGBO INSTITUTE OF MATERIALS TECHNOLOGY & ENGINEERING, CHINESE ACADEMY OF SCIENCES, NINGBO JUHUA CHEMICAL & SCIENCE CO., LTD.
    Inventors: Yexin Zhang, Qiang Zhou, Jian Zhang, Junliang Zhong, Xiuxiu Wang, Jili Du, Hui Chen, Chengjun Mu, Jie Yang, Linbing Xia, Yong Yang, Gang Wu
  • Publication number: 20240070364
    Abstract: An integrated circuit includes a first power rail and a second power rail extending in a first direction, and a first power grid stub connected to the first power rail through a first via-connector. The integrated circuit also includes a first vertical conducting line extending in a second direction in a circuit cell between a first vertical cell boundary and a second vertical cell boundary. The first vertical conducting line and the first power grid stub are in a same metal layer and aligned with each other along the second direction.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Johnny Chiahao LI, Sheng-Hsiung CHEN, Hui-Zhong ZHUANG, Jerry Chang Jui KAO, Xiangdong CHEN, Chung-Hsing WANG
  • Publication number: 20240072517
    Abstract: Provided is an elliptical multi-mesa laser structure, including a substrate layer, an N-DBR, a functional layer and a P-DBR sequentially arranged from bottom to top. The substrate layer is fixedly connected with an N contact layer. The N-DBR is fixedly connected to a top of the substrate layer, and the N contact layer is arranged around the N-DBR. A space layer is inserted in the N-DBR. The functional layer is fixedly connected to a top of the N-DBR. The P-DBR is fixedly connected to a top of the functional layer, and a top of the P-DBR is fixedly connected with a P contact layer. Another space layer is inserted into the P-DBR.
    Type: Application
    Filed: July 1, 2023
    Publication date: February 29, 2024
    Inventors: Hui LI, Jian FENG, Chuyu ZHONG, Wei MIAO, Shilong ZHAO, Zhao CHEN
  • Patent number: 11916058
    Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Lun Chien, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11916074
    Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin
  • Patent number: 11908851
    Abstract: A method for forming a semiconductor device includes: forming a fin structure protruding from a substrate of the semiconductor device; forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a first recess and a second recess; forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the first recess, wherein the first conductive line extends across the fin structure and wraps a portion of the fin structure; and forming a second conductive line in the same layer as the first conductive rail by filling a second conductive material into the second recess, wherein the second conductive line extends across the fin structure and contacts another portion of the fin structure.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shun-Li Chen, Chung-Te Lin, Hui-Zhong Zhuang, Pin-Dai Sue, Jung-Chan Yang
  • Patent number: 11907633
    Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Patent number: 11894383
    Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pochun Wang, Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien