Patents by Inventor Hui Zhong

Hui Zhong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230385504
    Abstract: A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured as a non-functional circuit. The first circuit includes a first pin and a second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes designating the first pin and the second pin as a first group of pins that are to be connected together. Placing the first cell layout by the APR tool includes connecting the first pin and the second pin in the first group of pins together thereby changing the first circuit to a second circuit. The second circuit is configured as a functional version of the first circuit.
    Type: Application
    Filed: August 23, 2022
    Publication date: November 30, 2023
    Inventors: Johnny Chiahao LI, Jung-Chan YANG, Jian-Sing LI, Hui-Zhong ZHUANG, Jerry Chang Jui KAO, Xiangdong CHEN
  • Patent number: 11830869
    Abstract: An integrated circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor includes a first active area extending in a first direction in a first layer. The second transistor includes a second active area that is disposed in a second layer below the first layer and overlaps the first active area. The third transistor includes at least two third active areas extending in the first direction in the first layer. In the first direction, a boundary line of one of the at least two third active areas is aligned with boundary lines of the first and second active areas. The fourth transistor includes at least two fourth active areas that are disposed in the second layer and overlap the at least two third active areas.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Sing Li, Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Publication number: 20230377976
    Abstract: An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 23, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui KAO, Hui-Zhong ZHUANG, Li-Chung HSU, Sung-Yen YEH, Yung-Chen CHIEN, Jung-Chan YANG, Tzu-Ying LIN
  • Publication number: 20230378267
    Abstract: A semiconductor device includes: fins configured to include: first active fins having a first conductivity type; and second active fins having a second conductivity type; and at least one gate structure formed over corresponding ones of the fins; and wherein the fins and the at least one gate structure are located in at least one cell region; and each cell region, relative to the second direction, including: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 23, 2023
    Inventors: Jung-Chan YANG, Hui-Zhong ZHUANG, Lee-Chung LU, Ting-Wei CHIANG, Li-Chun TIEN
  • Publication number: 20230372330
    Abstract: Disclosed herein are methods of treating a complication of a hemolysis and/or an inflammasome activation-associated disease comprising administering to a patient in need thereof quinine, or a derivative or salt thereof, or the combination of quinine and hemin. Also disclosed is a method of reducing alloimmunization in chronically transfused subjects, comprising administering to a patient in need thereof a therapeutically effective dose of quinine.
    Type: Application
    Filed: October 13, 2021
    Publication date: November 23, 2023
    Inventors: Hui Zhong, Karina Yazdanbakhsh
  • Publication number: 20230376668
    Abstract: A method of generating an IC layout diagram includes overlapping a channel region of an upper transistor of a complementary field-effect transistor (CFET) in an IC layout with a gate region of the CFET, thereby defining a channel overlap region, positioning an isolation region in the IC layout, the isolation region including an entirety of the channel overlap region, intersecting the isolation region with a conductive region, and generating an IC layout diagram based on the IC layout.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Shih-Wei PENG, Guo-Huei WU, Wei-Cheng LIN, Hui-Zhong ZHUANG, Jiann-Tyng TZENG
  • Publication number: 20230376672
    Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Hui-Zhong ZHUANG, Ting-Wei CHIANG, Li-Chun TIEN, Shun Li CHEN, Lee-Chung LU
  • Publication number: 20230359803
    Abstract: An integrated circuit structure includes a first, second and third power rail extending in a first direction, a first, second and third set of conductive structures extending in the second direction, and being located at a second level, and a first, second and third conductive structure extending in the second direction, and being located at a third level. The first conductive structure overlaps a first conductive structure of the corresponding first, second and third set of conductive structures. The second conductive structure overlaps a second conductive structure of the corresponding first, second and third set of conductive structures. The third conductive structure overlaps a third conductive structure of the corresponding first, second and third set of conductive structures.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Inventors: Jung-Chan YANG, Ting-Wei CHIANG, Cheng-I HUANG, Hui-Zhong ZHUANG, Chi-Yu LU, Stefan RUSU
  • Publication number: 20230361105
    Abstract: An integrated circuit (IC) device includes a substrate, at least one active region over the substrate and elongated along a first axis, at least one gate region extending across the at least one active region, and at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to other circuitry. The at least one IO pattern extends obliquely to the at least one active region or the at least one gate region.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 9, 2023
    Inventors: Wei-Ren CHEN, Cheng-Yu LIN, Hui-Zhong ZHUANG, Yung-Chen CHIEN, Jerry Chang Jui KAO, Huang-Yu CHEN, Chung-Hsing WANG
  • Patent number: 11811407
    Abstract: A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jin-Wei Xu, Hui-Zhong Zhuang, Chih-Liang Chen
  • Publication number: 20230343784
    Abstract: An integrated circuit is provided and includes first and second gates arranged in first and second layers, wherein the first and second gates extend in a first direction; a first insulating layer interposed between the first and second gates, wherein the first insulating layer, a first portion of the first gate, and a first portion of the second gate overlap with each other in a layout view; a cut layer, different from the first insulating layer, disposed on a second portion of the first gate; a first via passing through the cut layer and coupled to the second portion of the first gate; and a second via overlapping the first portion of the first gate and the first portion of the second gate, and coupled to the second gate. The first and second vias are configured to transmit different control signals to the first and second gates.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guo-Huei WU, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
  • Publication number: 20230343775
    Abstract: A method for semiconductor manufacturing is provided. The method includes defining a first cell level group comprising a first set of pattern features corresponding to a predetermined manufacturing process associated with an layout; determining a first number of cell units based on the first cell level group, wherein each of the first number of cell units is compatible with each other; defining a second cell level group comprising the first set of pattern features and a second set of pattern features; and determining a second number of cell units based on the second cell level group, wherein each of the second number of cell units is compatible with each other. The first set of pattern features and the second set of pattern features are arranged in responsive to sequential operations of the predetermined manufacturing process.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Inventors: CHUN-CHI TSAI, JUNG-CHAN YANG, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN
  • Publication number: 20230334208
    Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheok-Kei LEI, Zhe-Wei JIANG, Chi-Yu LU, Yi-Hsin KO, Chi-Lin LIU, Hui-Zhong ZHUANG
  • Patent number: 11791213
    Abstract: A system includes a non-transitory storage medium encoded with a set of instructions and a processor. The processor is configured to execute the set of instructions. The set of instructions is configured to cause the processor to: obtain, based on a netlist of a circuit, values each corresponding to one of transistors included in the circuit; compare the values with a threshold value; in response to a comparison, generate an adjusted netlist of the circuit by adding redundant transistors; and determine, based on the adjusted netlist, one of layout configurations for the circuit. The layout configurations include first cell rows each having a first row height and second cell rows each having a second row height different from the first row height.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Li-Chung Hsu, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang, Tzu-Ying Lin
  • Patent number: 11790148
    Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Zhong Zhuang, Ting-Wei Chang, Lee-Chung Lu, Li-Chun Tien, Shun Li Chen
  • Patent number: 11790151
    Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
  • Publication number: 20230326963
    Abstract: A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 12, 2023
    Inventors: JUNG-CHAN YANG, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN, TING-WEI CHIANG, CHENG-I HUANG, KUO-NAN YANG
  • Patent number: 11783109
    Abstract: A method of forming an IC device includes creating a recess by removing at least a portion of a channel of a first transistor and a portion of a gate electrode, the gate electrode being common to the first transistor and an underlying second transistor. The method includes filling the recess with a dielectric material to form an isolation layer, and constructing a slot via overlying the isolation layer.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Guo-Huei Wu, Wei-Cheng Lin, Hui-Zhong Zhuang, Jiann-Tyng Tzeng
  • Patent number: 11775727
    Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
  • Publication number: 20230305864
    Abstract: A method includes: different window display schemes may be automatically switched based on different scenarios. Specifically, a plurality of windows to be displayed on a display are grouped based on at least one of refresh rates of the plurality of windows, a quantity of the windows, sizes of the windows, locations, and the like, and a lane for transmitting window data is allocated to each window group obtained after grouping, so that window data of each window group can be refreshed, drawn, rendered, and presented based on a refresh rate required by the window data, and there is no need to present all the windows at a highest refresh rate.
    Type: Application
    Filed: July 9, 2021
    Publication date: September 28, 2023
    Inventors: Hui Zhong, Xiao Xiao