Abstract: A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate.

Abstract: The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer.

Abstract: Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. Compared with conventional approaches to form contacts, the present disclosure reduces contact resistance and avoids a short circuit between a gate and contact plugs, while simplifying manufacturing process, increasing integration density, and lowering manufacture cost. According to the manufacturing method of the present disclosure, second shallow trench isolations are formed with an upper surface higher than an upper surface of the source/drain regions. Regions defined by sidewall spacers of the gate, sidewall spacers of the second shallow trench isolations, and the upper surface of the source/drain regions are formed as contact holes. The contacts are formed by filling the contact holes with a conductive material. The method omits the steps of etching for providing the contact holes, which lowers manufacture cost.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region.

Abstract: The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region.

Abstract: A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost.

Abstract: Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer; then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate.

Abstract: The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.

Abstract: The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same.

Abstract: The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.

Abstract: The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

Abstract: The present invention provides a semiconductor device structure and a method for manufacturing the same. The method comprises: providing a semiconductor substrate, forming a first insulating layer on the surface of the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a stripe-type trench embedded in the first insulating layer and the semiconductor substrate; forming a channel region in the trench; forming a gate stack line on the channel region and source/drain regions on opposite sides of the channel region. Embodiments of the present invention are applicable to manufacture of semiconductor devices.

Abstract: An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In one aspect, the method comprises forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask. Then, forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. Then, removing a portion of the second shielding layer which is next to the other of the source and drain regions. Lastly, forming a first gate dielectric layer, a floating gate layer, and a second gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.

Abstract: A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate; conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure; and selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure. A semiconductor device manufactured by this process.