Abstract: Disclosed is an ML attack resisting method for a strong PUF. Response signals generated by applying multiple sets of different challenge signals to a strong PUF are used as information to be encrypted, and are put in order to form a plaintext matrix. Then a matrix multiplication operation is performed on two plaintext matrixes to generate a ciphertext matrix. Next, elements in a transform matrix obtained by performing binary transformation on the ciphertext matrix are used as final responses, which are in one-to-one correspondence with original challenge signals and are used as final CRPs of the matrix-encrypted strong PUF.

Abstract: The disclosure discloses a method for defending control flow attacks. When a data processor gives a response to an interrupt routine, a return address and a binary key are input to an encryption circuit to be encrypted to obtain an encrypted return address, and the obtained encrypted return address is synchronously written into a stack of the data processor and an built-in register bank; when the response given to the interrupt routine by the data processor is finished, the encrypted return address is read from the tack of the data processor and the built-in register bank; afterwards, the two encrypted return addresses are decrypted by first and second decryption circuits respectively to obtain two decrypted return addresses; and the two decrypted return addresses are compared to draw a conclusion whether the data process suffers from a control flow attack, and data processor determines to continue or terminate the routine accordingly.

Abstract: The invention discloses a circuit aging detection sensor based on voltage comparison. A control circuit generates an aging voltage signal, a standard voltage signal and a reference voltage signal. The aging voltage signal passes through a first voltage-controlled oscillator to generate an aging frequency signal. The standard voltage signal passes through a second voltage-controlled oscillator to generate a standard frequency signal. The standard frequency signal and the aging frequency signal pass through an aging detection circuit to generate a frequency difference signal. A level signal generated by a serial data detector passes through a beat-frequency oscillator to generate a reset signal. A counter quantizes aging information, which is converted by a digital-analog converter into a quantized voltage signal. The quantized voltage signal is compared with the reference voltage signal by a voltage comparator, to generate a hopping signal at a voltage superposition node, and an aging signal is output.

Abstract: A domino full adder based on delayed gating positive feedback comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter.

Abstract: The disclosure discloses a lookup table-based circuit aging detection sensor, including a control circuit, two voltage controlled oscillators (VCOs), two shaping circuits, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array and a digital-analogue converter. The control circuit respectively connects with the phase comparator, the 3-digit voter, the 8-digit counter, the first and the second VCOs. The first and second VCOs connect with the first and second shaping circuits respectively. The first and second shaping circuits connect with the phase comparator. The phase comparator connects with the 3-digit voter. The 3-digit voter connects with the beat-frequency oscillator. The beat-frequency oscillator respectively connects with the 8-digit counter and the latch. The 8-digit counter connects with the latch. The latch connects with the lookup table array. The lookup table array connects with the digital-analogue converter.

Abstract: A true random number generator based on a voltage-controlled oscillator includes a thermal noise generator, a ring oscillator, a voltage-controlled oscillator, a D flip-flop, and a post-processing circuit. The D flip-flop has a clock terminal, an input terminal, and an output terminal. An output terminal of the thermal noise generator is connected with an input terminal of the voltage-controlled oscillator. An output terminal of the voltage-controlled oscillator is connected with the clock terminal of the D flip-flop. An output terminal of the ring oscillator is connected with the input terminal of the D flip-flop. The output terminal of the D flip-flop is connected with an input terminal of the post-processing circuit. An input terminal of the thermal noise generator is connected with a reference level. The thermal noise generator includes a digital-analog converter, an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor.

Abstract: A domino full adder based on delayed gating positive feedback comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter.

Abstract: The invention discloses a circuit aging detection sensor based on voltage comparison. A control circuit generates an aging voltage signal, a standard voltage signal and a reference voltage signal. The aging voltage signal passes through a first voltage-controlled oscillator to generate an aging frequency signal. The standard voltage signal passes through a second voltage-controlled oscillator to generate a standard frequency signal. The standard frequency signal and the aging frequency signal pass through an aging detection circuit to generate a frequency difference signal. A level signal generated by a serial data detector passes through a beat-frequency oscillator to generate a reset signal. A counter quantizes aging information, which is converted by a digital-analog converter into a quantized voltage signal. The quantized voltage signal is compared with the reference voltage signal by a voltage comparator, to generate a hopping signal at a voltage superposition node, and an aging signal is output.

Abstract: A positive feedback XOR/XNOR gate and a low-delay hybrid logic adder are provided. The low-delay hybrid logic adder comprises the positive feedback XOR/XNOR gate and an output circuit. The positive feedback XOR/XNOR gate comprises a first PMOS transistor and a second PMOS transistor used as pass transistors, a first NMOS transistor and a second NMOS transistor constituting a pull-down network, and a third PMOS transistor, a third NMOS transistor and a fourth NMOS transistor constituting a positive feedback loop. When an XOR logic output terminal of the positive feedback XOR/XNOR gate is pulled down below a switching threshold of an inverter formed by the third PMOS transistor and the fourth NMOS transistor, the positive feedback loop starts to operate to enable the XOR logic output terminal of the positive feedback XOR/XNOR gate to enter a pull-down phase to be pulled down to a low level to avoid threshold voltage losses.

Abstract: The disclosure discloses a method for defending control flow attacks. When a data processor gives a response to an interrupt routine, a return address and a binary key are input to an encryption circuit to be encrypted to obtain an encrypted return address, and the obtained encrypted return address is synchronously written into a stack of the data processor and an built-in register bank; when the response given to the interrupt routine by the data processor is finished, the encrypted return address is read from the tack of the data processor and the built-in register bank; afterwards, the two encrypted return addresses are decrypted by first and second decryption circuits respectively to obtain two decrypted return addresses; and the two decrypted return addresses are compared to draw a conclusion whether the data process suffers from a control flow attack, and data processor determines to continue or terminate the routine accordingly.

Abstract: A true random number generator based on a voltage-controlled oscillator includes a thermal noise generator, a ring oscillator, a voltage-controlled oscillator, a D flip-flop, and a post-processing circuit. The D flip-flop has a clock terminal, an input terminal, and an output terminal. An output terminal of the thermal noise generator is connected with an input terminal of the voltage-controlled oscillator. An output terminal of the voltage-controlled oscillator is connected with the clock terminal of the D flip-flop. An output terminal of the ring oscillator is connected with the input terminal of the D flip-flop. The output terminal of the D flip-flop is connected with an input terminal of the post-processing circuit. An input terminal of the thermal noise generator is connected with a reference level. The thermal noise generator includes a digital-analog converter, an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor.

Abstract: A multi-port PUF circuit based on MOSFET current division deviations comprises a reference source, a row decoder, a column decoder, a timing controller and 32 PUF arrays. Each PUF array comprises 512 PUF cells arranged in 128 rows and 4 columns, an arbiter, a 1st inverter, a 2nd inverter, a 3rd inverter, a 4th inverter and eight transmission gates. The reference source is connected to the PUF arrays. The mth output terminal of the row decoder is connected to the mth row selective signal input terminals of the 32 PUF arrays. The jth output terminal of the column decoder is connected to the jth selective signal input terminals of the 32 PUF arrays. The 1st output terminal of the timing controller is connected to the control terminal of the row decoder. The 2nd output terminal of the timing controller is connected to the control terminal of the column decoder. The multi-port PUF circuit has the advantages of small circuit area and low power consumption while ensuring circuit performance.

Abstract: The disclosure discloses a lookup table-based circuit aging detection sensor, including a control circuit, two voltage controlled oscillators (VCOs), two shaping circuits, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array and a digital-analogue converter. The control circuit respectively connects with the phase comparator, the 3-digit voter, the 8-digit counter, the first and the second VCOs. The first and second VCOs connect with the first and second shaping circuits respectively. The first and second shaping circuits connect with the phase comparator. The phase comparator connects with the 3-digit voter. The 3-digit voter connects with the beat-frequency oscillator. The beat-frequency oscillator respectively connects with the 8-digit counter and the latch. The 8-digit counter connects with the latch. The latch connects with the lookup table array. The lookup table array connects with the digital-analogue converter.

Abstract: Disclosed is a lightweight bistable PUF circuit, comprising a decoding circuit, a timing control circuit, a PUF cell array and n sharing foot circuits. The PUF cell array is formed by m*n PUF cells arrayed in m lines and n columns. Each PUF cell includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, and the four PMOS transistors have the minimum width-to-length ratio of 120 nm/60 nm under a TSMC 65 nm process. Each sharing foot circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first two-input NAND gate and a second two-input NAND gate, and the four NMOS transistors have a width-to-length ratio ranging from 2 um/60 nm to 8 um/60 nm. The lightweight bistable PUF circuit has a reset function and the advantages of small area, low power consumption, small time delay and high speed.

Abstract: A static memory cell capable of balancing bit line leakage currents is characterized by including a 1st PMOS transistor, a 2nd PMOS transistor, a 1st NMOS transistor, a 2nd NMOS transistor, a 3rd NMOS transistor, a 4th NMOS transistor, a 5th NMOS transistor, a 6th NMOS transistor, a 7th NMOS transistor, an 8th NMOS transistor, a write word line, a read word line, a read bit line, an inverted read bit line, a write bit line and an inverted write bit line. The 1st NMOS transistor, the 2nd NMOS transistor, the 3rd NMOS transistor and the 4th NMOS transistor are all normal threshold NMOS transistors. The 1st PMOS transistor and the 2nd PMOS transistor are both low threshold PMOS transistors. The 5th NMOS transistor, the 6th NMOS transistor, the 7th NMOS transistor and the 8th NMOS transistor are all low threshold NMOS transistors. The static memory cell has the advantages of high read operation speed, low power consumption and high stability under low operating voltage conditions.

Abstract: A static memory cell capable of balancing bit line leakage currents is characterized by including a 1st PMOS transistor, a 2nd PMOS transistor, a 1st NMOS transistor, a 2nd NMOS transistor, a 3rd NMOS transistor, a 4th NMOS transistor, a 5th NMOS transistor, a 6th NMOS transistor, a 7th NMOS transistor, an 8th NMOS transistor, a write word line, a read word line, a read bit line, an inverted read bit line, a write bit line and an inverted write bit line. The 1st NMOS transistor, the 2nd NMOS transistor, the 3rd NMOS transistor and the 4th NMOS transistor are all normal threshold NMOS transistors. The 1st PMOS transistor and the 2nd PMOS transistor are both low threshold PMOS transistors. The 5th NMOS transistor, the 6th NMOS transistor, the 7th NMOS transistor and the 8th NMOS transistor are all low threshold NMOS transistors. The static memory cell has the advantages of high read operation speed, low power consumption and high stability under low operating voltage conditions.

Abstract: A ternary sense amplifier and an SRAM array realized by the ternary sense amplifier are provided. The ternary sense amplifier comprises the 1st CNFET transistor, the 2nd CNFET transistor, the 3rd CNFET transistor, the 4th CNFET transistor, the 5th CNFET transistor, the 6th CNFET transistor, the 7th CNFET transistor, the 8th CNFET transistor, the 9th CNFET transistor, the 10th CNFET transistor, the 11th CNFET transistor, the 12th CNFET transistor and the 13th CNFET transistor; the SRAM array comprises a ternary sense amplifier, a ternary memory array, the 1st inverter, the 2nd inverter, the 3rd inverter, the 4th inverter, the 14th CNFET transistor, the 15th CNFET transistor, the 16th CNFET transistor, the 17th CNFET transistor, the 18th CNFET transistor and the 19th CNFET transistor; it features in low power consumption, less postponement and high yield of chips.

Abstract: A current-mode PUF circuit based on a reference current source comprises an input register, the reference current source, a deviation current comparator and a timing controller. The input register is used for ensuring synchronization of the input challenges to avoid influences of asynchronous challenges on output responses. The reference current source generates a reference current for temperature and voltage compensation. A deviation current source array generates two paths of deviation currents under the control of the input challenges. The deviation current comparator generates and outputs a judgement according to the magnitude of the current provided by the deviation current source array. The timing controller is used for generating timing information for operation of the PUF circuit. The invention has the following advantages: the deviation current source array outputs deviation currents with high robustness and high reliability.

Abstract: A current-mode PUF circuit based on a reference current source comprises an input register, the reference current source, a deviation current comparator and a timing controller. The input register is used for ensuring synchronization of the input challenges to avoid influences of asynchronous challenges on output responses. The reference current source generates a reference current for temperature and voltage compensation. A deviation current source array generates two paths of deviation currents under the control of the input challenges. The deviation current comparator generates and outputs a judgement according to the magnitude of the current provided by the deviation current source array. The timing controller is used for generating timing information for operation of the PUF circuit. The invention has the following advantages: the deviation current source array outputs deviation currents with high robustness and high reliability.

Abstract: A multi-port PUF circuit based on MOSFET current division deviations comprises a reference source, a row decoder, a column decoder, a timing controller and 32 PUF arrays. Each PUF array comprises 512 PUF cells arranged in 128 rows and 4 columns, an arbiter, a 1st inverter, a 2nd inverter, a 3rd inverter, a 4th inverter and eight transmission gates. The reference source is connected to the PUF arrays. The mth output terminal of the row decoder is connected to the mth row selective signal input terminals of the 32 PUF arrays. The jth output terminal of the column decoder is connected to the jth selective signal input terminals of the 32 PUF arrays. The 1st output terminal of the timing controller is connected to the control terminal of the row decoder. The 2nd output terminal of the timing controller is connected to the control terminal of the column decoder. The multi-port PUF circuit has the advantages of small circuit area and low power consumption while ensuring circuit performance.