Abstract: A display method, including: performing a full-screen display refresh on a display panel at a first refresh rate; meanwhile, setting a refresh factor to n, where n is a positive integer; refreshing the local area of the display panel at the second refresh rate; increasing the refresh factor by m, where m is a positive integer; determining whether the refresh factor is greater than or equal to a set value; if yes, performing the full-screen display refresh on the display panel at the first refresh rate; setting the refresh factor to n; and if no, continuing refreshing the same local area of the display panel at the second refresh rate; increasing the refresh factor by m, where the second refresh rate is greater than the first refresh rate, and the second refresh rate is an integer multiple of the first refresh rate.

Abstract: A display module includes a display panel, at least one bonding circuit board, a plurality of chip-on-films, and a plurality of buffer devices. The at least one bonding circuit board each include first differential lines, and a first differential line includes a P-polarity differential sub-line and an N-polarity differential sub-line. An end of a chip-on-film is connected to the first differential line, and the other end of the chip-on-film is connected to the display panel. The buffer devices are arranged on the bonding circuit board, a buffer device is connected to ends, proximate to the chip-on-film, of the P-polarity differential sub-line and the N-polarity differential sub-line, and the buffer device is configured to reduce signal reflection between the first differential line and the chip-on-film.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof, including: a substrate; a plurality of transistors, arranged based on a first preset pattern; a plurality of transistor contact structures, corresponding to the transistors, the bottom portions of the transistor contact structures are arranged based on the first preset pattern, and top portions of which are arranged based on the shape of a regular hexagon; a plurality of memory cells, corresponding to the transistor contact structures, the memory cells are arranged based on the shape of a regular hexagon; and a plurality of memory contact structures, corresponding to the memory cells, the bottom portions of the memory contact structures are arranged based on the shape of a regular hexagon, top portions of which are arranged based on a second preset pattern, and the second preset pattern is different from the first preset pattern.

Abstract: Genome-wide data is obtained, and data cleansing, data sparsity processing and bioinformatics feature extraction are performed on the obtained genome-wide data; model construction is performed based on the sparsity-processed genome-wide data and the bioinformatics features to obtain a preliminary hybrid model; model training, regularization, and interpretability enhancement are performed on the preliminary hybrid model to obtain a trained model weight and an interpretability analysis corresponding to the trained model weight; learning and uncertainty estimation are performed based on the trained model weight and to-be-predicted genome-wide data on the hybrid model to obtain an integrated prediction result and uncertainties corresponding to the integrated prediction result; and personalized medical advice and decision assistance are performed based on the integrated prediction result, the interpretability analysis, and the uncertainties corresponding to the integrated prediction result.

Abstract: A display method, including: performing a full-screen display refresh on a display panel at a first refresh rate; meanwhile, setting a refresh factor to n, where n is a positive integer; refreshing the local area of the display panel at the second refresh rate; increasing the refresh factor by m, where m is a positive integer; determining whether the refresh factor is greater than or equal to a set value; if yes, performing the full-screen display refresh on the display panel at the first refresh rate; setting the refresh factor to n; and if no, continuing refreshing the same local area of the display panel at the second refresh rate; increasing the refresh factor by m, where the second refresh rate is greater than the first refresh rate, and the second refresh rate is an integer multiple of the first refresh rate.

Abstract: The present disclosure provides a semiconductor structure, a method of reading data from the semiconductor structure, and a method of writing data into the semiconductor structure. The semiconductor structure includes: a memory matrix, including a plurality of magnetic storage domains arranged in a staggered manner and including a first end, a second end, and an intermediate portion; and a reading and writing circuit, connected to the intermediate portion of the memory matrix and configured to write data into the magnetic storage domains and read data from the magnetic storage domains.

Abstract: A method for manufacturing a semiconductor structure includes the following: providing a substrate; forming an MTJ structure and a first mask structure in sequence on the substrate; performing a patterning process on the first mask structure to form a first pattern extending in a first direction; transferring the first pattern to the MTJ structure; forming a second mask structure on the MTJ structure; performing a patterning process on the second mask structure to form a second pattern extending in a second direction, the first direction intersecting the second direction and being not perpendicular to the second direction; and performing a patterning process on the MTJ structure by utilizing the second pattern to form a cellular MTJ array, the first pattern and the second pattern together forming a cellular pattern.

Abstract: An image dis play method applied to a display apparatus includes: establishing a correspondence table between a threshold voltage of a sub-pixel and a compensation voltage, the correspondence table including at least one adjustment interval, an adjustment interval including a first and second threshold voltage endpoint values, the first threshold voltage endpoint value being less than the second threshold voltage endpoint value; acquiring a threshold voltage of each sub-pixel; determining an adjustment interval in which the acquired threshold voltage is located according to the corresponding table; acquiring a compensation voltage corresponding to the acquired threshold voltage according to the correspondence table and the determined adjustment interval; and determining, in a case where the display apparatus is to display a black image, a data voltage required by each sub-pixel according to the acquired threshold voltage and the acquired compensation voltage.

Abstract: A vertical transistor, and a memory cell and a manufacturing method therefor are provided. The vertical transistor includes: a source electrode disposed on a substrate; a drain electrode which is disposed at a side, away from the substrate, of the source electrode; and a gate electrode and a semiconductor layer, which are in the same layer, and are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to the substrate. The gate electrode at least comprises a column-shaped first gate electrode extending in the first direction. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.

Abstract: Provided is a compensation method for a display device. The method includes: acquiring first detection voltages of the plurality of subpixels during a first shutdown compensation process; acquiring first position indication information based on the first detection voltages of the plurality of subpixels; and determining first compensation data based on the first position indication information. The first position indication information indicates column positions of pixels to which a plurality of first subpixels of the plurality of subpixels belong. The first compensation data includes first threshold compensation voltages of the plurality of subpixels, and an absolute value of a difference between the first threshold compensation voltage of the first subpixel and a first reference value is less than an absolute value of a difference between a second threshold compensation voltage of the first subpixel in the first compensation data and the first reference value.

Abstract: The present disclosure provides a chip on film and a display device. The chip on film includes: a first end, wherein a first row of bonding terminals and a second row of bonding terminals are arranged on a first surface of the first end, the first row of bonding terminals and the second row of bonding terminals are spaced apart and insulated from each other, and the first row of bonding terminals is closer to a center of the chip on film than the second row of bonding terminals; and a plurality of leads, extending in a second direction and including a first part and a second part. A first end section of each lead of the first part serves as one of the first row of bonding terminals, a first end section of each lead of the second part serves as one of the second row of bonding terminals.

Abstract: A display module includes a display panel, at least one bonding circuit board, a plurality of chip-on-films, and a plurality of buffer devices. The at least one bonding circuit board each include first differential lines, and a first differential line includes a P-polarity differential sub-line and an N-polarity differential sub-line. An end of a chip-on-film is connected to the first differential line, and the other end of the chip-on-film is connected to the display panel. The buffer devices are arranged on the bonding circuit board, a buffer device is connected to ends, proximate to the chip-on-film, of the P-polarity differential sub-line and the N-polarity differential sub-line, and the buffer device is configured to reduce signal reflection between the first differential line and the chip-on-film.

Abstract: A display module includes a display panel, a power supply driver, a voltage signal line, a sampling resistor and a detection and control circuit. The voltage signal line is connected between the display panel and the power supply driver. The sampling resistor is connected in series with the voltage signal line. The detection and control circuit is connected to two ends of the sampling resistor and the power supply driver. The detection and control circuit is configured to: detect a voltage across the sampling resistor or a current flowing through the sampling resistor; and control the power supply driver to generate a driving voltage equal to a preset value lower than a voltage threshold, if determining that the voltage across the sampling resistor is greater than or equal to the voltage threshold, or if determining that the current is greater than or equal to a current threshold.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a transistor; a first phase change memory structure, a bottom electrode of the first phase change memory structure being electrically connected to a first terminal (source or drain) of the transistor; a second phase change memory structure, a top electrode of the second phase change memory structure being electrically connected to the first terminal of the transistor; a first bit line, electrically connected to a top electrode of the first phase change memory structure; and a second bit line, electrically connected to a bottom electrode of the second phase change memory structure.

Abstract: An image dis play method applied to a display apparatus includes: establishing a correspondence table between a threshold voltage of a sub-pixel and a compensation voltage, the correspondence table including at least one adjustment interval, an adjustment interval including a first and second threshold voltage endpoint values, the first threshold voltage endpoint value being less than the second threshold voltage endpoint value; acquiring a threshold voltage of each sub-pixel; determining an adjustment interval in which the acquired threshold voltage is located according to the corresponding table; acquiring a compensation voltage corresponding to the acquired threshold voltage according to the correspondence table and the determined adjustment interval; and determining, in a case where the display apparatus is to display a black image, a data voltage required by each sub-pixel according to the acquired threshold voltage and the acquired compensation voltage.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a transistor, including a control terminal, a first terminal, and a second terminal; a first magnetic memory structure, a bottom electrode of which is electrically connected to the first terminal of the transistor; a second magnetic memory structure, a top electrode of which is electrically connected to the first terminal of the transistor, the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure; a first bit line, electrically connected to a top electrode of the first magnetic memory structure; a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and a selection line, electrically connected to a second terminal of the transistor.

Abstract: Provided is a packaging structure for packaging a display device, the packaging structure comprising: at least one composite film layer, wherein the composite film layer comprises an inorganic pattern and an organic pattern, the inorganic pattern comprises a plurality of curved structures arranged at intervals, the organic pattern comprises a first organic sub-pattern, and the first organic sub-pattern and the inorganic pattern are located in a same layer and are complementary in position; and wherein an orthographic projection of the composite film layer onto the display device at least covers a display area of the display device. A display substrate, a display apparatus, and a method for packaging a display device are also provided.

Abstract: The present disclosure provides a semiconductor structure, a method of reading data from the semiconductor structure, and a method of writing data into the semiconductor structure. The semiconductor structure includes: a memory matrix, including a plurality of magnetic storage domains arranged in a staggered manner and including a first end, a second end, and an intermediate portion; and a reading and writing circuit, connected to the intermediate portion of the memory matrix and configured to write data into the magnetic storage domains and read data from the magnetic storage domains.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including active regions arranged at intervals, where the active region includes a source, a drain, and a channel region; a word line, where the word line is connected to the channel region and extends along a first direction; a bit line, where the bit line is connected to the drain or the source and extends along a second direction, the first direction being different from the second direction; and a magnetic memory cell, connected to the source or the drain.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof, including: a substrate; a plurality of transistors, arranged based on a first preset pattern; a plurality of transistor contact structures, corresponding to the transistors, the bottom portions of the transistor contact structures are arranged based on the first preset pattern, and top portions of which are arranged based on the shape of a regular hexagon; a plurality of memory cells, corresponding to the transistor contact structures, the memory cells are arranged based on the shape of a regular hexagon; and a plurality of memory contact structures, corresponding to the memory cells, the bottom portions of the memory contact structures are arranged based on the shape of a regular hexagon, top portions of which are arranged based on a second preset pattern, and the second preset pattern is different from the first preset pattern.