Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate. A plurality of vertical transistors arranged in an aligned manner are formed on the substrate, wherein a channel material of the vertical transistor includes an oxide semiconductor. A plurality of staggered contact pads connected to upper ends of the vertical transistors are formed on the vertical transistors, wherein a single contact pad is connected to the upper ends of an even number of vertical transistors. A magnetic tunnel junction is formed on the contact pad.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a plurality of memory cells alternately arranged on a substrate, the memory cell including an odd number of vertical transistors, a connection pad connected to one end of each of the odd number of vertical transistors, and a magnetic tunnel junction located on the connection pad; wherein a material of a channel of the vertical transistor includes a monocrystalline semiconductor.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and a memory. The semiconductor structure may at least include: a plurality of transistors arranged in a staggered manner, wherein the transistors share one source plate, a channel of the transistor is located on the source plate, and a channel length direction of the transistor is perpendicular to a surface of the source plate, and a material of the channel includes an oxide semiconductor; a plurality of drain contact members, electrically connected to drains of the transistors, wherein an odd number of transistors share one drain contact member, and the transistors sharing the same drain contact member are driven by a same word line; and a plurality of magnetic tunnel junctions, located on the drain contact members, wherein the magnetic tunnel junctions are electrically connected to the drain contact members in a one-to-one corresponding manner.

Abstract: A method for manufacturing a semiconductor structure includes the following: providing a substrate; forming an MTJ structure and a first mask structure in sequence on the substrate; performing a patterning process on the first mask structure to form a first pattern extending in a first direction; transferring the first pattern to the MTJ structure; forming a second mask structure on the MTJ structure; performing a patterning process on the second mask structure to form a second pattern extending in a second direction, the first direction intersecting the second direction and being not perpendicular to the second direction; and performing a patterning process on the MTJ structure by utilizing the second pattern to form a cellular MTJ array, the first pattern and the second pattern together forming a cellular pattern.

Abstract: A semiconductor structure, a manufacturing method therefor and a memory are provided. The semiconductor structure may at least include: a plurality of aligned transistors, in which the transistors share a same source plate, channels of the transistors are located above the source plate, the channel length direction of the transistors is perpendicular to a surface of the source plate, and a material of the channels includes a single crystal semiconductor; a plurality of drain contacts, electrically connected with drains of the transistors, in which even number of the transistors share one same drain contact; and a plurality of magnetic tunnel junctions, located on the drain contacts and electrically connected with the drain contacts in one-to-one correspondence.

Abstract: The present application relates to a memory device and a preparing method thereof. The memory device includes: a substrate, and a plurality of memory cells disposed in an array on the substrate. Memory cells in adjacent rows are staggered in a row direction, and a distance between two adjacent memory cells in any row is a first distance. Memory cells in adjacent columns are staggered in a column direction, and a staggered distance is less than the first distance.

Abstract: A method for manufacturing a semiconductor structure, a semiconductor structure and a semiconductor memory are provided. The method includes: providing a substrate; forming an MTJ structure and a first mask structure sequentially on the substrate; patterning the first mask structure to form a first pattern extending in a first direction; forming a second mask structure on the first pattern; patterning the second mask structure to form a second pattern extending in a second direction, in which the first direction intersects the second direction, and is not perpendicular to the second direction; patterning the first pattern by utilizing the second pattern to form a cellular pattern; and transferring the cellular pattern to the MTJ structure to form a cellular MTJ array.

Abstract: A semiconductor structure includes: a Magnetic Random Access Memory (MRAM) cell, including a bottom electrode, a Magnetic Tunnel Junction (MTJ) stack and a top electrode; an insulating layer covering a sidewall partially and a top surface of the MRAM cell; a first dielectric layer, a stop layer and a second dielectric layer sequentially stacked on the insulating layer; and a top electrode contact hole penetrating through the second dielectric layer, the stop layer, the first dielectric layer and the insulating layer, and extending to the top electrode, where the top electrode contact hole includes a first portion and a second portion connected with each other in the stop layer, and a radial width of the second portion in contact with the top electrode is gradually decreased with an increase in a depth of the top electrode contact hole. Method for manufacturing the structure and semiconductor memory are also provided.

Abstract: The present disclosure relates to an array substrate, a display device, and a method for fabricating an array substrate. The array substrate includes a pixel defining layer on the dielectric layer, the pixel defining layer defining a plurality of pixel regions of the array substrate, and light emitting device on the dielectric layer and in the plurality of pixel regions. The device includes a first electrode, a light emitting layer, and a second electrode sequentially disposed from bottom to top. At least one of the plurality of pixel regions has a non-light emitting region adjacent to the pixel defining layer. The dielectric layer in the non-light emitting region has a groove. The array substrate further includes a light shielding portion located in the non-light emitting region and extending into the groove.

Abstract: Embodiments of the present disclosure provide a method of manufacturing a magnetic random access memory (MRAM) and a MRAM. The method includes: preparing a bottom electrode through hole, a bottom electrode, a magnetic tunnel junction (MTJ), a top electrode, and an insulating layer sequentially on a semiconductor substrate; forming a first interlayer dielectric layer on the insulating layer; forming an etching stop layer on the first interlayer dielectric layer; forming a second interlayer dielectric layer on the etching stop layer; etching a part of the second interlayer dielectric layer above the top electrode to the etching stop layer, and forming a first trench; performing a self-alignment implantation inclined on a part of the first interlayer dielectric layer corresponding to a bottom of the first trench; continuously etching through the first trench to a top end surface of the top electrode, and forming a second trench.

Abstract: The embodiment of the present disclosure provides a display panel and a display device. The display panel includes: a first sub-pixel configured to display a first color, a second sub-pixel configured to display a second color, and a third sub-pixel configured to display a third color; when a picture displayed by the display panel is switched from a black picture to a picture having a maximum gray scale of the first color, the second color and the third color, respectively, a ratio of a brightness of a first frame of picture to a maximum value among brightness of stabilized several frames of pictures is a first initial frame brightness proportion, a second initial frame brightness proportion and a third initial frame brightness proportion, respectively; the first, second and third initial frame brightness proportions have a Max-Min less than or equal to a threshold.

Abstract: A display module includes a display panel, a power supply driver, a voltage signal line, a sampling resistor and a detection and control circuit. The voltage signal line is connected between the display panel and the power supply driver. The sampling resistor is connected in series with the voltage signal line. The detection and control circuit is connected to two ends of the sampling resistor and the power supply driver. The detection and control circuit is configured to: detect a voltage across the sampling resistor or a current flowing through the sampling resistor; and control the power supply driver to generate a driving voltage equal to a preset value lower than a voltage threshold, if determining that the voltage across the sampling resistor is greater than or equal to the voltage threshold, or if determining that the current is greater than or equal to a current threshold.

Abstract: The embodiment of the present disclosure provides a display panel and a display device. The display panel includes: a first sub-pixel configured to display a first color, a second sub-pixel configured to display a second color, and a third sub-pixel configured to display a third color; when a picture displayed by the display panel is switched from a black picture to a picture having a maximum gray scale of the first color, the second color and the third color, respectively, a ratio of a brightness of a first frame of picture to a maximum value among brightness of stabilized several frames of pictures is a first initial frame brightness proportion, a second initial frame brightness proportion and a third initial frame brightness proportion, respectively; the first, second and third initial frame brightness proportions have a Max-Min less than or equal to a threshold.

Abstract: The present disclosure provides a chip on film and a display device. The chip on film includes: a first end, wherein a first row of bonding terminals and a second row of bonding terminals are arranged on a first surface of the first end, the first row of bonding terminals and the second row of bonding terminals are spaced apart and insulated from each other, and the first row of bonding terminals is closer to a center of the chip on film than the second row of bonding terminals; and a plurality of leads, extending in a second direction and including a first part and a second part. A first end section of each lead of the first part serves as one of the first row of bonding terminals, a first end section of each lead of the second part serves as one of the second row of bonding terminals.

Abstract: Provided is a micro-LED device, comprising: a light emitting unit comprising a light emitting layer having a first end surface, a second end surface opposite to the first end surface, and a lateral surface between the first end surface and the second end surface; a P-type semiconductor layer on the first end surface; and an N-type semiconductor layer on the second end surface; a transparent insulating layer covering at least the lateral surface of the light emitting layer; and a reflecting layer on a side of the transparent insulating layer away from the light emitting unit, wherein the transparent insulating layer insulates the light emitting unit from the reflecting layer, and the reflecting layer covers at least the lateral surface of the light emitting layer.

Abstract: The present disclosure provides a light emitting device, a display substrate and a display equipment. The light emitting device includes: a light emitting layer, the light emitting layer including a host material including an aggregation-induced delayed fluorescent material and a guest material including at least one of a fluorescent material or a phosphorescent material.

Abstract: An array substrate is disclosed. The array substrate may include a base substrate (21), a pixel defining layer (22) on the base substrate (21), and a charge generating layer (24) above the pixel defining layer (22). The pixel defining layer (22) may define a plurality of pixel regions. The pixel defining layer (22) may include a plurality of acoustic structures (220), and each of the plurality of acoustic structures (220) may be configured to resonate under an action of an acoustic wave of a threshold frequency to form a slit to disconnect the charge generating layer (24) of two adjacent pixel regions of the plurality of pixel regions.

Abstract: A display panel and a manufacturing method thereof, and a display device are disclosed. The display panel includes: a substrate, a plurality of pixel units and a pixel defining layer, each of at least one of the pixel units comprises an organic functional layer, and the organic functional layer has a raised edge; an orthographic projection of the organic functional layer of each pixel unit on the substrate is surrounded by an orthographic projection of the second defining layer on the substrate, an orthographic projection of the first defining layer on the substrate covers the orthographic projection of the second defining layer on the substrate, and the orthographic projection of the first defining layer on the substrate overlaps with an orthographic projection of at least a portion of the raised edge on the substrate the brightness uniformity of the display panel may be improved.

Abstract: The present application provides a pixel compensation circuit, a method for driving the same, and a display apparatus. The pixel compensation circuit includes a light emitting element, a current control sub-circuit and a reverse bias sub-circuit. The current control sub-circuit is coupled to a first terminal of the light emitting element and is configured to control current flowing between a first terminal and a second terminal of the light emitting element. The reverse bias sub-circuit is coupled to a first control signal line and a second terminal of the light emitting element respectively. The reverse bias sub-circuit is configured to set the second terminal of the light emitting element to be at a first bias voltage under the control of a signal on the first control signal line, so that the light emitting element is maintained in a reverse bias state.

Abstract: A pixel circuit is provided. A first terminal and a second terminal of a light-emitting sub-circuit are coupled to a first power supply terminal and a compensation sub-circuit respectively. A short-circuiting sub-circuit is coupled to the first terminal and the second terminal of, and short-circuits under control of a short-circuiting control terminal, the light-emitting sub-circuit. The compensation sub-circuit is coupled to a data voltage terminal, a reference voltage terminal, and a first electrode and a gate electrode of a driving transistor. The light-emitting sub-circuit emits a light of brightness in a level corresponding to a current flowing therethrough. The compensation sub-circuit loads, based on the data voltage terminal and the reference voltage terminal, a driving voltage related to a threshold voltage of the driving transistor onto the gate electrode of the driving transistor, such that a current flowing through the driving transistor is not influenced by its threshold voltage.