Abstract: The embodiments of the present invention disclose a low temperature (LTPS) transistor array substrate and a method of fabricating the same, and a display device. The LTPS transistor array substrate comprises a substrate; a poly-silicon semiconductor active region provided on the substrate; agate insulated from the poly-silicon semiconductor active region; and a dielectric spacer region provided on a side wall of the gate, wherein a portion of the poly-silicon semiconductor active region corresponding to the dielectric spacer region comprises a buffer region, and the dielectric spacer region surrounds the side wall of the gate and covers the buffer region.

Abstract: A manufacturing method of a low temperature polycrystalline silicon thin film and a manufacturing method of a thin film transistor are provided. The manufacturing method of the low temperature polycrystalline silicon thin film comprises: forming an amorphous silicon thin film on a substrate; and performing a rapid thermal annealing (RTA) process on the amorphous silicon thin film for several times at a predetermined temperature to form the low temperature polycrystalline silicon thin film, wherein the predetermined temperature is lower than a conventional RTA crystallization temperature.

Abstract: A method for preparing an LTPS membrane, including: forming an amorphous silicon (a-Si) layer (S3) on a substrate (S1) by a patterning process, in which the a-Si layer (S3) comprises a plurality of convex structures (S32) and etched areas (S31) which are disposed along circumference of the plurality of convex structures and partially etched; and performing excimer laser crystallization (ELC) on the a-Si layer (S3) and obtaining the LTPS membrane. A thin-film transistor (TFT) and a display device are further disclosed, which are used for overcoming poor uniformity of the polysilicon membrane prepared by the ELC technology.

Abstract: In various embodiments, an optical alignment structure may be provided. The optical alignment structure may include a light carrying structure configured to receive an input optical light from an external light source. The optical alignment structure may further include a light redirection mechanism coupled to the light carrying structure. The light redirection mechanism may be configured to receive the input optical light from the light carrying structure. The light redirection mechanism may be further configured to redirect the input optical light back to the light carrying structure, the redirected input optical light configured to be detected by a detector for alignment of the optical alignment structure with the external optical source.

Abstract: A manufacturing method of a low temperature polycrystalline silicon thin film and a manufacturing method of a thin film transistor are provided. The manufacturing method of the low temperature polycrystalline silicon thin film comprises: forming an amorphous silicon thin film on a substrate; and performing a rapid thermal annealing (RTA) process on the amorphous silicon thin film for several times at a predetermined temperature to form the low temperature polycrystalline silicon thin film, wherein the predetermined temperature is lower than a conventional RTA crystallization temperature.

Abstract: According to embodiments of the present invention, an alignment method for a silicon photonics packaging is provided. The method includes providing a plurality of waveguides, each of the plurality of waveguides including an input and an output, arranging a light source relative to the plurality of waveguides, the light source being configured to provide an input light to the input of at least one of the plurality of waveguides, detecting respective output light intensity exiting the outputs of the plurality of waveguides, and identifying based on the detected output light intensity a selected waveguide of the plurality of waveguides for subsequent coupling.

Abstract: A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the skeleton specifies cell placements and associated bounding boxes for the cell placements, but does not include geometries for the cell placements. The system then computes environments for cell placements based on the skeleton. Next, the system generates templates for cell placements, wherein a template for a cell placement specifies the cell placement and the environment surrounding the cell placement. The system then generates the simulated wafer image by performing model-based simulations for cell placements associated with unique templates.

Abstract: A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the skeleton specifies cell placements and associated bounding boxes for the cell placements, but does not include geometries for the cell placements. The system then computes environments for cell placements based on the skeleton. Next, the system generates templates for cell placements, wherein a template for a cell placement specifies the cell placement and the environment surrounding the cell placement. The system then generates the simulated wafer image by performing model-based simulations for cell placements associated with unique templates.