Patents by Inventor Hun-Hyeong Lim
Hun-Hyeong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11916240Abstract: A secondary battery includes: an electrode assembly including electrode sheets and a separator interposed between the electrode sheets; a pouch-like battery casing in which the electrode assembly is received; an electrode lead connected to the electrode assembly and protruding out from the battery casing; and a lead film covering the electrode lead and interposed between the electrode lead and the battery casing, wherein the lead film includes an outer layer covering the electrode lead and an inner layer disposed inside of the outer layer, and the inner layer includes a material having a higher air permeability as compared to the outer layer.Type: GrantFiled: December 8, 2021Date of Patent: February 27, 2024Assignee: LG Energy Solution, Ltd.Inventors: Hun-Hee Lim, Sang-Hun Kim, Min-Hyeong Kang, Hyung-Kyun Yu
-
Patent number: 10224185Abstract: A substrate processing apparatus including a process chamber configured to receive a plurality of substrates oriented in a horizontal manner and vertically arranged with respect to the process chamber, a process gas supply unit configured to supply at least one process gas to the process chamber through a process gas supply nozzle, the process gas supply nozzle along an inner wall of the process chamber in a direction in which the substrates are sacked, an exhaust unit configured to exhaust the process gas from the process chamber, and a blocking gas supply unit configured to supply a blocking gas through a blocking gas injector provided in a circumferential direction of the process chamber such that a flow of the process gas in the process chamber is controlled may be provided.Type: GrantFiled: April 17, 2015Date of Patent: March 5, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Young-jin Noh, Kwang-min Park, Eun-sung Seo, Young-chang Song, Jae-young Ahn, Hun-hyeong Lim, Ji-hoon Choi
-
Patent number: 9991281Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.Type: GrantFiled: August 8, 2017Date of Patent: June 5, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Mi Yun, Young-Jin Noh, Kwang-Min Park, Jae-Young Ahn, Guk-Hyon Yon, Dong-Chul Yoo, Joong-Yun Ra, Young-Seon Son, Jeon-Il Lee, Hun-Hyeong Lim
-
Publication number: 20170358596Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.Type: ApplicationFiled: August 8, 2017Publication date: December 14, 2017Inventors: JU-MI YUN, Young-Jin Noh, Kwang-Min Park, Jae-Young Ahn, Guk-Hyon Yon, Dong-Chul Yoo, Joong-Yun Ra, Young-Seon Son, Jeon-Il Lee, Hun-Hyeong Lim
-
Patent number: 9793291Abstract: A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.Type: GrantFiled: April 29, 2016Date of Patent: October 17, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Jin Shin, Hong-Suk Kim, Jung-Hwan Kim, Sang-Hoon Lee, Hun-Hyeong Lim, Yong-Seok Cho, Young-Dae Kim, Han-Vit Yang
-
Patent number: 9754959Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.Type: GrantFiled: December 9, 2015Date of Patent: September 5, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Mi Yun, Young-Jin Noh, Kwang-Min Park, Jae-Young Ahn, Guk-Hyon Yon, Dong-Chul Yoo, Joong-Yun Ra, Young-Seon Son, Jeon-Il Lee, Hun-Hyeong Lim
-
Patent number: 9653472Abstract: According to example embodiments, a method of fabricating a semiconductor device includes alternately stacking interlayer insulating layers and intermediate layers on a substrate, forming openings passing through the interlayer insulating layers and the intermediate layers to form recessed regions in the substrate, forming first epitaxial layers on recessed surfaces in the recessed regions, and forming second epitaxial layers using the first epitaxial layers as seed layers. The second epitaxial layers fill the recessed regions and extend above the substrate.Type: GrantFiled: March 13, 2015Date of Patent: May 16, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Woong Lee, Chae Ho Kim, Kyong Won An, Joon Suk Lee, Woo Sung Lee, Hun Hyeong Lim
-
Patent number: 9536896Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.Type: GrantFiled: March 31, 2015Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Hoon Lee, Jin-Gyun Kim, Hyun Namkoong, Ki-Hyun Hwang, Hun-Hyeong Lim, Dong-Kyum Kim
-
Publication number: 20160343729Abstract: A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.Type: ApplicationFiled: April 29, 2016Publication date: November 24, 2016Inventors: Hyun-Jin SHIN, Hong-Suk KIM, Jung-Hwan KIM, Sang-Hoon LEE, Hun-Hyeong LIM, Yong-Seok CHO, Young-Dae KIM, Han-Vit YANG
-
Patent number: 9490140Abstract: There are provided methods for manufacturing a semiconductor device including providing a substrate including a metal layer including an oxidized surface layer in a heat treatment chamber, generating hydrogen radicals within the heat treatment chamber and reducing the oxidized surface layer of the metal layer using the hydrogen radicals.Type: GrantFiled: August 24, 2015Date of Patent: November 8, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun Yong Go, Eun Young Lee, Jung Geun Jee, Eun Yeoung Choi, Jin Gyun Kim, Hun Hyeong Lim
-
Patent number: 9461061Abstract: A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.Type: GrantFiled: November 18, 2014Date of Patent: October 4, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Jin-Gyun Kim, Jae-Young Ahn, Hun Hyeong Lim, Ki-Hyun Hwang
-
Patent number: 9431416Abstract: A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first interlayer insulating layers. The gate layers and the first interlayer insulating layers are alternately and vertically stacked on each other. The first stacked structure is disposed on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second interlayer insulating layers. The first sacrificial layers and the second interlayer insulating layers are alternately and vertically stacked on each other. The second stacked structure is disposed on a second sidewall of the first vertical channel structure. The first sacrificial layers is formed of a polysilicon layer.Type: GrantFiled: October 28, 2014Date of Patent: August 30, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil-ouk Nam, Jun-kyu Yang, Hun-hyeong Lim, Ki-hyun Hwang, Jae-young Ahn, Dong-chul Yoo
-
Publication number: 20160172372Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.Type: ApplicationFiled: December 9, 2015Publication date: June 16, 2016Inventors: JU-MI YUN, YOUNG-JIN NOH, KWANG-MIN PARK, JAE-YOUNG AHN, GUK-HYON YON, DONG-CHUL YOO, JOONG-YUN RA, YOUNG-SEON SON, JEON-IL LEE, HUN-HYEONG LIM
-
Publication number: 20160168704Abstract: A gas injector may comprise: a gas introduction tube configured to introduce reaction gas into a reaction tube from a gas supply source; and/or a gas distributor connected to the gas introduction tube, extending from the gas introduction tube in a direction within the reaction tube, including a plurality of ejection holes in an inner surface of the gas distributor, and having an arc shape extending in a circumferential direction of the reaction tube. The ejection holes may be spaced apart from each other in the extending direction of the gas distributor, and are configured to spray the reaction gas.Type: ApplicationFiled: December 9, 2015Publication date: June 16, 2016Inventors: Ji-Hoon CHOI, Young-Jin NOH, Joong-Yun RA, Jae-Young AHN, Hun-hyeong LIM
-
Publication number: 20160071877Abstract: A semiconductor device can include a single crystalline silicon substrate and a plurality of peripheral region circuits on the single crystalline silicon substrate. An insulating layer can be on the plurality of peripheral region circuits and a polycrystalline silicon substrate can be on the insulating layer, where the polycrystalline silicon substrate can include a first layer of the polycrystalline silicon substrate and an epi-second layer of the polycrystalline silicon substrate on the first layer. A plurality of memory cell circuits can be on the polycrystalline silicon substrate.Type: ApplicationFiled: September 4, 2015Publication date: March 10, 2016Inventors: DONG WOO KIM, DONG KYUM KIM, HUN HYEONG LIM, JUNG GEUN LEE
-
Publication number: 20160064190Abstract: A substrate processing apparatus including a process chamber configured to receive a plurality of substrates oriented in a horizontal manner and vertically arranged with respect to the process chamber, a process gas supply unit configured to supply at least one process gas to the process chamber through a process gas supply nozzle, the process gas supply nozzle along an inner wall of the process chamber in a direction in which the substrates are sacked, an exhaust unit configured to exhaust the process gas from the process chamber, and a blocking gas supply unit configured to supply a blocking gas through a blocking gas injector provided in a circumferential direction of the process chamber such that a flow of the process gas in the process chamber is controlled may be provided.Type: ApplicationFiled: April 17, 2015Publication date: March 3, 2016Inventors: Young-jin NOH, Kwang-min PARK, Eun-sung SEO, Young-chang SONG, Jae-young AHN, Hun-hyeong LIM, Ji-hoon CHOI
-
Publication number: 20160064227Abstract: There are provided methods for manufacturing a semiconductor device including providing a substrate including a metal layer including an oxidized surface layer in a heat treatment chamber, generating hydrogen radicals within the heat treatment chamber and reducing the oxidized surface layer of the metal layer using the hydrogen radicals.Type: ApplicationFiled: August 24, 2015Publication date: March 3, 2016Inventors: Hyun Yong GO, Eun Young LEE, Jung Geun JEE, Eun Yeoung CHOI, Jin Gyun KIM, Hun Hyeong LIM
-
Patent number: 9276133Abstract: A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.Type: GrantFiled: February 19, 2014Date of Patent: March 1, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hwan Kim, Jun-Kyu Yang, Hun-Hyeong Lim, Jae-ho Choi, Ki-Hyun Hwang
-
Publication number: 20160056169Abstract: According to example embodiments, a method of fabricating a semiconductor device includes alternately stacking interlayer insulating layers and intermediate layers on a substrate, forming openings passing through the interlayer insulating layers and the intermediate layers to form recessed regions in the substrate, forming first epitaxial layers on recessed surfaces in the recessed regions, and forming second epitaxial layers using the first epitaxial layers as seed layers. The second epitaxial layers fill the recessed regions and extend above the substrate.Type: ApplicationFiled: March 13, 2015Publication date: February 25, 2016Inventors: Woong LEE, Chae Ho KIM, Kyong Won AN, Joon Suk LEE, Woo Sung LEE, Hun Hyeong LIM
-
Publication number: 20150206901Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.Type: ApplicationFiled: March 31, 2015Publication date: July 23, 2015Inventors: SANG-HOON LEE, JIN-GYUN KIM, KOONG-HYUN NAM, KI-HYUN HWANG, HUN-HYEONG LIM, DONG-KYUM KIM