Patents by Inventor HUNG AN KAO

HUNG AN KAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130105926
    Abstract: A manufacturing method of a BSI image sensor includes providing a substrate having a plurality of photo-sensing elements and a plurality of multilevel interconnects formed on a first side of the substrate; forming a redistribution layer (RDL) and a first insulating layer covering the RDL on the front side of the substrate; providing a carrier wafer formed on the front side of the substrate; forming a color filter array (CFA) on a second side of the substrate, the second side being opposite to the first side; removing the carrier wafer; and forming a first opening in the first insulating layer for exposing the RDL.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 2, 2013
    Inventor: Ching-Hung Kao
  • Publication number: 20130069190
    Abstract: An image sensor comprises a substrate, a plurality of photoelectric transducer devices, an interconnect structure, at least one dielectric isolator and a back-side alignment mark. The substrate has a front-side surface and a back-side surface opposite to the front-side surface. The interconnect structure is disposed on the front-side surface. The photoelectric transducer devices are formed on the front-side surface. The dielectric isolator extends downwards into the substrate from the back-side surface in order to isolate the photoelectric transducer devices. The back-side alignment mark extends downwards into the substrate from the back-side surface and references to a front-side alignment mark previously formed on the front-side surface.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 21, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Ching-Hung KAO, Hsin-Ping Wu
  • Publication number: 20130069189
    Abstract: A bonding pad structure is used in an integrated circuit device. The integrated circuit device includes a semiconductor substrate with a first surface and a second surface. The bonding pad structure includes a dielectric layer, a conductor structure, a pad opening and an isolation trench. The dielectric layer is formed on the second surface of the semiconductor substrate. The conductor structure is disposed within the dielectric layer. The pad opening is formed in the first surface of the semiconductor substrate. The pad opening runs through the semiconductor substrate and a part of the dielectric layer, so that the conductor structure is exposed. The isolation trench has an opening in the first surface of the semiconductor substrate. The isolation trench runs through the semiconductor substrate and a part of the dielectric layer, and the isolation trench is disposed around the pad opening.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 21, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventor: Ching-Hung Kao
  • Publication number: 20130049849
    Abstract: A filter system capable of automatically adjusting bandwidth includes a filter and an adaptive unit. The filter is used for filtering a digital signal to generate an output signal to an application unit. The adaptive unit is used for generating an adjustment signal to the filter according to the digital signal and the output signal. The filter dynamically adjusts bandwidth of the filter according to the adjustment signal.
    Type: Application
    Filed: February 6, 2012
    Publication date: February 28, 2013
    Inventor: Ping-Hung Kao
  • Patent number: 8383448
    Abstract: A method of fabricating an MOS device is provided. First, gates and source/drain regions of transistors are formed on a substrate. A photodiode doped region and a floating node doped region are formed in the substrate. Thereafter, a spacer stacked layer including a bottom layer, an inter-layer and a top layer is formed to cover each gate of the transistors. Afterwards, a first mask layer having an opening exposing at least the photodiode doped region is formed on the substrate, and then the top layer exposed by the opening is removed. Next, the first mask layer is removed, and then a second mask layer is formed on a region correspondingly exposed by the opening. A portion of the top layer and the inter-layer exposed by the second mask layer is removed to form spacers on sidewalls of the gates.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: February 26, 2013
    Assignee: United Microelectronics Corp.
    Inventor: Ching-Hung Kao
  • Publication number: 20130034949
    Abstract: A method of forming trench isolation with different depths of a semiconductor device is disclosed. A semiconductor substrate having a first mask layer formed thereon is first provided. A first etching process is performed with the first mask layer as an etching mask to form a shallow trench structure, followed by forming a first dielectric layer on the semiconductor substrate to fill the shallow trench structure. The first dielectric layer is then patterned to form a second mask layer which is used in a second etching process to form a deep trench structure. After that, a dielectric material is applied to fill the deep trench structure.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 7, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Hung KAO
  • Patent number: 8334189
    Abstract: A method for forming trench isolation on a substrate includes providing a substrate having thereon a pad layer and a hard mask; forming a first shallow trench in a first area and a second trench in a second area on the substrate; forming a resist layer covering the first area while exposing the second area; etching the second shallow trench to form a deep trench; forming oxide liner within the first shallow trench and the deep trench; and filling the shallow trench and the deep trench with an oxide layer.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: December 18, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Ching-Hung Kao
  • Patent number: 8329216
    Abstract: The invention pertains to a method of relieving pain by administering a controlled release pharmaceutical tablet containing oxymorphone which produces a mean minimum blood plasma level 12 to 24 hours after dosing, as well as the tablet producing the sustained pain relief.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: December 11, 2012
    Assignee: Endo Pharmaceuticals Inc.
    Inventors: Haui-Hung Kao, Anand R. Baichwal, Troy McCall, David Lee
  • Publication number: 20120287548
    Abstract: Disclosed is a surge protector which is provided before an electrical device to be protected for protecting the electrical device from harmful electrical disturbances, the surge protector comprises at least three terminals including a signal input terminal, a signal output terminal and grounding terminal; and the protector comprises; at least one circuit protecting module provided between the signal input terminal and the signal output terminal and electrically connected to the electrical device to be protected in series, thereby the circuit protecting module becomes an open circuit simultaneously when an applied voltage is greater than a safety threshold thereof in a normal mode to protect the electrical device; and at least one surge diverting module provided between an input of the circuit protecting module and the grounding terminal for directing energy of the surge to ground in a shunt mode.
    Type: Application
    Filed: September 20, 2011
    Publication date: November 15, 2012
    Inventor: Chih-Hung KAO
  • Patent number: 8309122
    Abstract: The invention pertains to a method of relieving pain by administering a controlled release pharmaceutical tablet containing oxymorphone which produces a mean minimum blood plasma level 12 to 24 hours after dosing, as well as the tablet producing the sustained pain relief.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: November 13, 2012
    Assignee: Endo Pharmaceuticals Inc.
    Inventors: Huai-Hung Kao, Anand R. Baichwal, Troy McCall, David Lee
  • Publication number: 20120267716
    Abstract: A high voltage metal oxide semiconductor device with low on-state resistance is provided. A multi-segment isolation structure is arranged under a gate structure and beside a drift region for blocking the current from directly entering the drift region. Due to the multi-segment isolation structure, the path length from the body region to the drift region is increased. Consequently, as the breakdown voltage applied to the gate structure is increased, the on-state resistance is reduced.
    Type: Application
    Filed: April 20, 2011
    Publication date: October 25, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Hung KAO, Sheng-Hsiong Yang
  • Publication number: 20120252832
    Abstract: Abuse-resistant, controlled release opioid tablets are a combination containing an opioid antagonist such as naloxone at a level above that needed to suppress the euphoric effect of the opioid, if the combination were crushed to break the controlled release properties causing the opioid and opioid antagonist to be released as an immediate release product as a single dose. The controlled release nature of the tablet prevents the accumulation of orally effective amounts of opioid antagonist when taken normally. The opioid antagonist is contained in a controlled-release matrix and released, over time, with the opioid.
    Type: Application
    Filed: June 12, 2012
    Publication date: October 4, 2012
    Applicant: Endo Pharmaceuticals Inc.
    Inventors: Frank S. Caruso, Huai-Hung Kao
  • Publication number: 20120237603
    Abstract: We provide a pharmaceutical dosage form including an opioid antagonist surrounded by a controlled release matrix and an opioid agonist in a surrounding matrix.
    Type: Application
    Filed: May 25, 2012
    Publication date: September 20, 2012
    Applicant: Endo Pharmaceuticals Inc.
    Inventors: Huai-Hung Kao, Yadi Zeng, Michelle Howard-Sparks, Fai Jim
  • Patent number: 8268662
    Abstract: A method of fabricating a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. First, an isolation structure is formed in a substrate with a photo-sensitive region and a transistor device region in the substrate. The transistor device region includes at least a region for forming a transfer transistor. A dielectric layer and a conductive layer are sequentially formed on the substrate. An ion implantation process is performed to implant a dopant into the substrate below the position for forming a gate of the transfer transistor and in the photo-sensitive region through the conductive layer and the dielectric layer. The conductive layer and the dielectric layer are patterned to at least form the gate structure of the transfer transistor on the transistor device region. Thereafter, a photo diode is formed in the substrate in the photo-sensitive region.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: September 18, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Ching-Hung Kao
  • Publication number: 20120231075
    Abstract: We provide a pharmaceutical dosage form including an opioid antagonist surrounded by a controlled release matrix and an opioid agonist in a surrounding matrix.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 13, 2012
    Applicant: Endo Pharmaceuticals Inc.
    Inventors: Huai-Hung Kao, Yadi Zeng, Michelle Howard-Sparks, Fai Jim
  • Publication number: 20120190168
    Abstract: A method for forming trench isolation on a substrate includes providing a substrate having thereon a pad layer and a hard mask; forming a first shallow trench in a first area and a second trench in a second area on the substrate; forming a resist layer covering the first area while exposing the second area; etching the second shallow trench to form a deep trench; forming oxide liner within the first shallow trench and the deep trench; and filling the shallow trench and the deep trench with an oxide layer.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 26, 2012
    Inventor: Ching-Hung Kao
  • Publication number: 20120108000
    Abstract: A method of fabricating an MOS device is provided. First, gates and source/drain regions of transistors are formed on a substrate. A photodiode doped region and a floating node doped region are formed in the substrate. Thereafter, a spacer stacked layer including a bottom layer, an inter-layer and a top layer is formed to cover each gate of the transistors. Afterwards, a first mask layer having an opening exposing at least the photodiode doped region is formed on the substrate, and then the top layer exposed by the opening is removed. Next, the first mask layer is removed, and then a second mask layer is formed on a region correspondingly exposed by the opening. A portion of the top layer and the inter-layer exposed by the second mask layer is removed to form spacers on sidewalls of the gates.
    Type: Application
    Filed: January 5, 2012
    Publication date: May 3, 2012
    Inventor: Ching-Hung Kao
  • Patent number: 8164620
    Abstract: A stereo projection optical system includes an image engine configured for providing light superimposed spatial information, a color selector positioned to receive a light output of the image engine, a transmission-type light modulator positioned to receive an emergent light of the color selector. The color selector is configured for selectively modifying the polarization of the light output according to the wavelength of the light output. The transmission-type light modulator alternates between a dark state and a bright state. From the foregoing, it will be apparent that the stereo projection optical system according to the present invention provides advantages in that its structure can be simplified with the reduction of its size by synthesizing lift and right image signals by displaying the stereoscopic image signal using a single projector.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: April 24, 2012
    Assignee: Hon Hai Precision Idnustry Co., Ltd.
    Inventors: Chien-Wen Hsu, Chia-Hung Kao, Huan-Liang Lo, Sheng-Chung Huang
  • Publication number: 20120018661
    Abstract: A water-saving valve assembly has a base, a control valve device and a buffer device. The control valve device is mounted in the base. The water-saving valve assembly is mounted on an exit of a water pipe. Users can control the flowing out or stopping of water in the water pipe via the control valve device. The buffer device provides a gradual effect of switching off and can effectively reduce positive and negative pressure waves generated in the water pipe. Noises and damage to the water pipe are also prevented.
    Type: Application
    Filed: February 12, 2010
    Publication date: January 26, 2012
    Applicant: HIGHPLUS INTERNATIONAL CO., LTD.
    Inventors: Chih-Hung Kao, Yu-Yueh Kao
  • Patent number: 8077196
    Abstract: A stereo projection optical system, includes a first polarizing beam splitter configured for separating a light input into a first polarized light component and a second polarized light component; a first transmission-type spatial light modulator configured for receiving the first polarized light component; a second transmission-type spatial light modulator configured for receiving the second polarized light component; a second polarizing beam splitter positioned to receive the light outputs of the first, second spatial light modulators. The first and second transmission-type spatial light modulators respectively generate two images formed by the first polarized light component and the second polarized light component with spatial information. When a viewer wears glasses that have two polarizing lenses whose polarization directions are perpendicular to each other, the viewer can perceive projected images as being three-dimensional.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: December 13, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Chia-Hung Kao, Chien-Wen Hsu