Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.

Abstract: A method includes forming an isolation region between a plurality of active regions of a semiconductor substrate, forming at least one deep trench extending from the isolation region toward a bottom of the semiconductor substrate, and forming an interlayer dielectric layer over the semiconductor substrate. The interlayer dielectric layer fills in the deep trench to form a deep trench isolation structure and an air void in the deep trench isolation structure.

Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.

Abstract: An improved impact massager includes two impact force modules and a main circuit board in a chassis. An electromagnetic component and a cushioning element are coaxially provided in a heat sink of each impact force module. A drive rod of a drive component group is connected to an impact rod. A coupler of a transmission assembly is connected to the coupling seat with an oscillating coil provided therein and electrically connected with the main circuit board. When the oscillating coil and the magnetic core ring are coaxially positioned and displaced with respect to each other, the magnetic core ring does not interact with the oscillating coil, no current is generated by the oscillating coil and the main circuit board is in a power-off state, such that no power is transmitted to the electromagnetic component and motions are inhibited under no-load condition.

Abstract: Embodiments herein beneficially enable simultaneous processing of a plurality of substrates in a digital direct write lithography processing system. In one embodiment a method of processing a plurality of substrate includes positioning a plurality of substrates on a substrate carrier of a processing system, positioning the substrate carrier under the plurality of optical modules, independently leveling each of the plurality of substrates, determining offset information for each of the plurality of substrates, generating patterning instructions based on the offset information for each of the plurality of substrates, and patterning each of the plurality of substrates using the plurality of optical modules. The processing system comprises a base, a motion stage disposed on the base, the substrate carrier disposed on the motion stage, a bridge disposed above a surface of the base and separated therefrom, and a plurality of optical modules disposed on the bridge.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region, a first active component and at least one deep trench isolation structure. The isolation region is in the semiconductor substrate. The first active component is on the semiconductor substrate. The deep trench isolation structure extends from a bottom of the isolation region toward a bottom of the semiconductor substrate. The deep trench isolation structure has at least one air void therein.

Abstract: Embodiments of the present disclosure generally provide a digital lithography system that can process both large area substrates as well as semiconductor device substrates, such as wafers. Both the large area substrates and the semiconductor device substrates can be processed in the same system simultaneously. Additionally, the system can accommodate different levels of exposure for forming the features over the substrates. For example, the system can accommodate very precise feature patterning as well as less precise feature patterning. The different exposures can occur in the same chamber simultaneously. Thus, the system is capable of processing both semiconductor device substrates and large area substrates simultaneously while also accommodating very precise feature patterning simultaneous with less precise feature patterning.

Abstract: Embodiments of the present disclosure generally provide a digital lithography system that can process both large area substrates as well as semiconductor device substrates, such as wafers. Both the large area substrates and the semiconductor device substrates can be processed in the same system simultaneously. Additionally, the system can accommodate different levels of exposure for forming the features over the substrates. For example, the system can accommodate very precise feature patterning as well as less precise feature patterning. The different exposures can occur in the same chamber simultaneously. Thus, the system is capable of processing both semiconductor device substrates and large area substrates simultaneously while also accommodating very precise feature patterning simultaneous with less precise feature patterning.

Abstract: The present invention is to provide a simultaneous interpretation method, comprising the steps of: acquiring an audio stream data input by a user into a simultaneous interpretation device; converting the audio stream data into textual data according to a source language, after acquiring the audio stream data; translating the textual data according to text corpuses in an optimized database that correspond to a target language in order to acquire a first translation text; transmitting the textual data to a third-party database in order for the third-party database to translate the textual data according to the target language, and acquiring a second translation text from the third-party database; and determining whether the first translation text is acquired; and if yes, converting the first translation text into an audio stream data and transmitting the audio stream data to the simultaneous interpretation device in order for the simultaneous interpretation device to output the audio stream data in voice; or if

Abstract: In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.

Abstract: A machine diagnostic system includes a performance evaluating module, a machine adjusting module and multiple sensors. The performance evaluating module evaluates the performance value of a part of a machine prior to production and predicts whether the part can be used to complete multiple batches of semi-products. If yes, the machine adjusting module sets a set value of the machine so that the machine can complete the multiple batches of semi-products. When the batches of semi-products are processed by the machine, a real-time production data is generated. When the sensors detect that the real-time production data contains an abnormal state data, re-evaluating whether the machine can complete the remaining semi-products according to the set value. If yes, enabling the machine to continue processing the remaining semi-products according to the set value. If no, updating the set value of the machine.

Abstract: A semiconductor wafer and a semiconductor wafer fabrication method are provided. The wafer includes a supporting substrate, a semiconductor substrate and a contact layer. The supporting substrate has a first surface and a second surface opposite to the first surface. The semiconductor substrate is disposed on the first surface of the supporting substrate, in which the semiconductor substrate is configured to form plural devices. The contact layer is disposed on the second surface of the supporting substrate to contact the supporting substrate, in which the contact layer is configured to contact an electrostatic chuck and has a resistivity of the contact layer smaller than a resistivity of the supporting substrate. In semiconductor wafer fabrication method, at first, a raw wafer is provided. Then, the contact layer is formed by using an implantation operation or a deposition operation.

Abstract: The semiconductor structure includes a semiconductor substrate; a first active region and a second active region on the semiconductor substrate and separated by an isolation feature; and a field-effect transistor formed on the semiconductor substrate. The field-effect transistor further includes a gate stack disposed on the semiconductor substrate and extending from the first active region to the second active region; and a source and a drain formed on the first active region and interposed by the gate stack. The semiconductor structure further includes a doped feature formed on the second active region and configured as a gate contact to the field-effect transistor.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region, a first active component and at least one deep trench isolation structure. The isolation region is in the semiconductor substrate. The first active component is on the semiconductor substrate. The deep trench isolation structure extends from a bottom of the isolation region toward a bottom of the semiconductor substrate. The deep trench isolation structure has at least one air void therein.

Abstract: Abuse-resistant, controlled release opioid tablets are a combination containing an opioid antagonist such as naloxone at a level above that needed to suppress the euphoric effect of the opioid, if the combination were crushed to break the controlled release properties causing the opioid and opioid antagonist to be released as a immediate release product as a single dose. The controlled release nature of the table prevents the accumulation of orally effective amounts of opioid antagonist when taken normally. The opioid antagonist is contained in a controlled-release matrix and released, over time, with the opioid.

Abstract: A method for dispensing photoresist over a semiconductor wafer is provided. The method includes moving a dispensing nozzle to a predetermined position where the longitudinal axis of the dispensing nozzle aligns with the central axis of the semiconductor wafer. The method further includes dispensing a chemical liquid over the semiconductor wafer via the dispensing nozzle. The method also includes dispensing a photoresist over the semiconductor wafer that is coated with the chemical liquid via the dispensing nozzle. During the dispensing of the chemical liquid and the photoresist, the dispensing nozzle stays in the predetermined position.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate. The substrate includes a first semiconductor layer, a second semiconductor layer, and an insulating layer between the first semiconductor layer and the second semiconductor layer. The semiconductor device structure also includes a gate stack over the substrate. The semiconductor device structure further includes source and drain structures in the second semiconductor layer of the substrate. The source and drain structures are on opposite sides of the gate stack. In addition, the semiconductor device structure includes a first isolation feature in the substrate. The first isolation feature includes an insulation material and surrounds the source and drain structures. The semiconductor device structure also includes a second isolation feature in the first isolation feature. The second isolation feature includes a metal material and surrounds the source and drain structures.

Abstract: A panel displaying method for an electronic device is provided. The electronic device includes a display module and has a plurality of first icons corresponding to a plurality of objects. The panel displaying method includes: determining an environment of the electronic device; automatically choosing an operation mode based on the environment of the electronic device. The operation mode is displayed in a widget area of a first panel and includes at least one widget icon. A portion of the first icons is chosen and updated as the widget icon based on numbers of clicks of the first icons in the chosen operation mode. Moreover, a portable electronic device and a recording medium using the method are also provided.

Abstract: An adjusting method is implemented by a control system and is used to adjust a multi-axis robotic arm including a plurality of motors. The adjusting method includes following operations. A decay rate of each motor is analyzed by the control system. When the decay rate of one of the motors exceeds a corresponding first threshold, a residual value of the one of the motors is further analyzed by the control system. When the residual value exceeds a first default value, an output capacity of at least one of the motors is adjusted by the control system.