Abstract: A class IV partial response, maximum likelihood data channel for a disk drive includes an encoder connected to a data sequencer for converting user data blocks into a predetermined 8/9ths code such as a (0,4,4,) code. A precoder conveys the 8/9ths code into class IV code. An analog write driver supplies the class IV code to a data transducer head during data write-to-disk operations. A read channel connected to the head amplifies and conditions analog signals during data read operations. A quantizer produces samples of the analog signals in accordance with a quantization clock generated by a clock generator. An adaptive FIR filter means is conditions the data samples in accordance with selectable, adaptive filter coefficients. A Viterbi detector puts out the class IV code from the filtered and quantized samples. A postcoder conveys the detected class IV code into detected 8/9ths code. A decoder converts the detected 8/9ths code into user data and supplies user data to the sequencer.

Abstract: An improved cross-checking circuit is provided for use within a Reed-Solomon error correction and cross checking apparatus for performing error correction and cross checking upon a data block within an incoming stream of substantially contiguous data blocks flowing from a source to a destination. The circuit is based upon a distinguished primitive element, alpha.sup.1 (2B (Hex))=x.sup.5 +x.sup.3 +x+1, of a Galois field whose elements are represented by residue classes of binary polynomials modulo p(x)=x.sup.8 +x.sup.4 +x.sup.3 +x.sup.2 +1. The apparatus includes a microcontroller for supervising the flow of the data blocks and for making calculations related to error corrections, and a Galois field syndrome generator and remainder recovery circuit is connected to receive the incoming stream and recover therefrom plural error correction remainder bytes for each block and selectively to hold said bytes in a syndrome latch, the remainder bytes being related to syndrome bytes appended to the data block.

Abstract: A digital adaptive finite impulse response filter circuit is provided for a PR4,ML sampled data channel including an analog to digital sampler for providing raw digital samples of data to the filter circuit and a sampled data detector for detecting coded data from conditioned digital samples received from the filter circuit. The filter circuit comprises a multi-tap transversal filter structure wherein each tap is connected to receive a selected coefficient, a source of a plurality of coefficients for each tap, a coefficient selector connected to the source to receive the plurality of coefficients and to provide a selected coefficient to each tap of the transversal filter structure, and a control circuit for controlling the coefficient selector and the source for providing each of the selected coefficients to a corresponding tap of the transversal filter structure. Training and adaptation methods and circuits for adapting the filter structure are also described.

Abstract: A multi-mode gain control loop for a PR4, ML data channel, such as one included in a magnetic disk data storage device, includes an input for receiving from a source an analog signal stream including coded data to be detected; a VGA for amplifying the analog signal stream; an analog to digital converter for receiving the analog signal stream and for generating and putting out data samples therefrom; an analog gain control loop connected to generate an analog gain control from the analog data stream during a data non-read mode of the channel, to store the analog gain control in a storage circuit, and to apply the stored analog gain control constantly to control the VGA; and a digital gain control loop connected to generate gain vernier correction values from the data samples and for applying the gain vernier correction values through a gain DAC to provide an offset control to the VGA during a data read mode of the channel.

Abstract: A class IV partial response, maximum likelihood data channel for a disk drive includes an encoder connected to a data sequencer for converting user data blocks into a predetermined 8/9ths code such as a (0,4,4,) code. A precoder converts the 8/9ths code into class IV code. An analog write driver supplies the class IV code to a data transducer head during data write-to-disk operations. A read channel connected to the head amplifies and conditions analog signals during data read operations. A quantizer produces samples of the analog signals in accordance with a quantization clock generated by a clock generator. An adaptive FIR filter means is conditions the data samples in accordance with selectable, adaptive filter coefficients. A Viterbi detector puts out the class IV code from the filtered and quantized samples. A postcoder converts the detected class IV code into detected 8/9ths code. A decoder converts the detected 8/9ths code into user data and supplies user data to the sequencer.

Abstract: A Viterbi detector for a PR4,ML data channel includes a data sample input for receiving digital data samples from a source. Digital data samples are taken of data which has been coded in a predetermined data code format and which has been passed through a data degrading channel. A delay circuit delays the digital data samples received at the data sample input. A delay selector controls an output of the delay circuit in accordance with a feedback control bit value. An adder circuit combines data samples from the data sample input with delayed samples from the delay circuit to produce a sum. A threshold input receives programmable positive and negative data threshold values. A threshold selector puts out either the positive or the negative threshold values in accordance with a sign bit control value. A comparator compares the sum with a selected threshold value and puts out a logical value based upon comparison thereof.

Abstract: A class IV partial response, maximum likelihood data channel for a disk drive includes an encoder connected to a data sequencer for converting user data blocks into a predetermined 8/9ths code such as a (0,4,4,) code. A precoder converts the 8/9ths code into class IV code. An analog write driver supplies the class IV code to a data transducer head during data write-to-disk operations. A read channel connected to the head amplifies and conditions analog signals during data read operations. A quantizer produces samples of the analog signals in accordance with a quantization clock generated by a clock generator. An adaptive FIR filter means is conditions the data samples in accordance with selectable, adaptive filter coefficients. A Viterbi detector puts out the class IV code from the filtered and quantized samples. A postcoder converts the detected class IV code into detected 8/9ths code. A decoder converts the detected 8/9ths code into user data and supplies user data to the sequencer.

Abstract: A digital peak detection circuit asynchronously detects embedded overhead information such as servo or sync pattern data within a PR4,ML synchronous data detection channel of a magnetic disk drive. The channel includes an analog to digital converter clocked by a data clock operating asynchronously with respect to playback of the embedded overhead information in the channel for converting an analog data stream into raw data samples, and an adaptive digital FIR filter for conditioning the raw data samples into conditioned data samples in accordance with programmable filter coefficients.

Abstract: A serializer/deserializer encoder-decoder for a disk drive achieves increased storage capacity through the use of partial response maximum likelihood class IV (PRML-IV) coding. Reduction of hardware requirements is realized by the integration of similar read and write mode functions into common circuit elements in order to reduce duplication. To this end, a data word selector selectively receives or sends data words in the write/read mode, respectively, from a data sequencer. Dependent upon the mode the data words are either provided to an encoder or received from a decoder for translation to/from code words. The encoder-decoder sends or receives the code words to a code word selector which in turn connects with the serializer-deserializer for coupling with the write or read channel.

Abstract: A multi-mode timing loop for a PR4,ML sampled data channel includes an analog to digital converter and a digital finite impulse response filter for providing conditioned digital samples. The timing loop includes a reference clock source for putting out a reference clock frequency related to a nominal sample data rate, a frequency controllable oscillator connected to generate a sample clock, an analog timing loop and a digital timing loop. The analog timing loop provides phase lock during non-data read mode, and during data read mode the digital timing loop provides a vernier offset for fine adjustment of phase lock to a static setting then provided by the analog timing loop.

Abstract: An on-the-fly error correction method and apparatus for correcting a data block within a stream of substantially contiguous data blocks during a data decoding process, each block having a Reed-Solomon error syndrome calculated and appended during an encoding process.

Abstract: The present invention relates to new compounds which are the 1,2-dihydro-4-methyl-1-oxo-5H-pyrido(4,3-b)indoles with the formula (I): ##STR1## in which R represents hydrogen or an alkoxy or aryl carbonyloxy group. These compounds are intermediates of synthesis in the preparation of compounds which can be used in the pharamaceutical industry. The invention is also concerned with their synthesis.