Patents by Inventor Hung Cai Ngo
Hung Cai Ngo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Storage Cell Design Evaluation Circuit Including a Wordline Timing and Cell Access Detection Circuit
Publication number: 20080137455Abstract: A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.Type: ApplicationFiled: December 12, 2006Publication date: June 12, 2008Inventors: Sebastian Ehrenreich, Jente B Kuang, Chun-Tao Li, Hung Cai Ngo -
Publication number: 20080130387Abstract: A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.Type: ApplicationFiled: April 27, 2007Publication date: June 5, 2008Inventors: Jente B. Kuang, Jerry C. Kao, Hung Cai Ngo, Kevin J. Nowka
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Patent number: 7349271Abstract: A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.Type: GrantFiled: October 13, 2005Date of Patent: March 25, 2008Assignee: International Business Machines CorporationInventors: Jente B. Kuang, Jerry C. Kao, Hung Cai Ngo, Kevin J. Nowka
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Patent number: 7272624Abstract: A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.Type: GrantFiled: September 30, 2003Date of Patent: September 18, 2007Assignee: International Business Machines CorporationInventors: Wendy Ann Belluomini, Hung Cai Ngo, Jun Sawada
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Patent number: 7202705Abstract: A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed version of the logic clock and turns on the output inverter foot device after the dynamic node has had sufficient time to evaluate, providing a fast evaluate time and reducing leakage through the inverter input when the foot device is off. Alternatively, a coarsely timed static power control signal may be used to control the inverter foot devices. The drains of the inverter foot devices can be commonly connected across multiple circuits, reducing the foot device total area.Type: GrantFiled: November 18, 2004Date of Patent: April 10, 2007Assignee: International Business Machines CorporationInventors: Hung Cai Ngo, Jente Benedict Kuang, Harmander Singh Deogun, AJ Kleinosowski
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Patent number: 7193446Abstract: A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except when required for a transition in the output of the dynamic circuit. The keeper circuit includes a transistor having a smaller area than a corresponding transistor in the output circuit, thus reducing leakage through the gate of the output circuit when the keeper circuit is holding the output and the output circuit foot device is disabled. A self-clocked control of the output circuit foot device can be provided via a delayed version of the dynamic logic gate output, or may be provided by an external control circuit that generates a delayed version of the precharge clock or a multi-cycle signal.Type: GrantFiled: November 18, 2004Date of Patent: March 20, 2007Assignee: International Business Machines corporationInventors: Hung Cai Ngo, Jente Benedict Kuang, Harmander Singh Deogun, AJ Kleinosowski
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Patent number: 7142015Abstract: A buffer, logic circuit, and data processing system employing fast turn-off drive circuitry for reducing leakage. Leakage current in logic circuitry is managed by coupling and decoupling the voltage potentials applied to large, high-leakage devices. Circuitry includes a low leakage logic path for holding logic states of an output after turning off high-leakage devices. A fast turn-off logic path in parallel with the low leakage logic path is used to assert each logic state in the forward direction from input to output. The large output device in each fast turn-off path is relieved of leakage stress by asserting logic states at driver inputs that cause the driver to turn OFF after the output logic state has been asserted.Type: GrantFiled: September 23, 2004Date of Patent: November 28, 2006Assignee: International Business Machines CorporationInventors: Jente Benedict Kuang, Hung Cai Ngo, Kevin John Nowka
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Patent number: 7088154Abstract: Methods and arrangements for a low power, phase-locked loop (PLL) are disclosed. Embodiments include a multi-phase oscillator like a voltage-controlled oscillator (VCO) to generate multiple phases of a clock signal. The multiple phases are then combined to generate a single clock signal having a frequency substantially equivalent to the number of phases multiplied by the frequency of the clock signal generated by the multi-phase VCO. Advantageously, embodiments can generate clock signals having frequencies that are multiples of the frequency generated by the VCO, reducing the power consumed by the VCO to produce a clock signal having the same frequency as a clock signal generated by a single phase VCO. Further, the achievable frequency for the VCO is increased. In many embodiments, a high speed, n-bit frequency divider that implements a pulse latch facilitates the use of the multi-phase VCO to generate the very high frequency clock signals.Type: GrantFiled: January 18, 2005Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventor: Hung Cai Ngo
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Patent number: 6943599Abstract: Methods and arrangements for a low power, phase-locked loop (PLL) are disclosed. Embodiments include a multi-phase oscillator like a voltage-controlled oscillator (VCO) to generate multiple phases of a clock signal. The multiple phases are then combined to generate a single clock signal having a frequency substantially equivalent to the number of phases multiplied by the frequency of the clock signal generated by the multi-phase VCO. Advantageously, embodiments can generate clock signals having frequencies that are multiples of the frequency generated by the VCO, reducing the power consumed by the VCO to produce a clock signal having the same frequency as a clock signal generated by a single phase VCO. Further, the achievable frequency for the VCO is increased. In many embodiments, a high speed, n-bit frequency divider that implements a pulse latch facilitates the use of the multi-phase VCO to generate the very high frequency clock signals.Type: GrantFiled: December 10, 2003Date of Patent: September 13, 2005Assignee: International Business Machines CorporationInventor: Hung Cai Ngo
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Patent number: 6891399Abstract: A clock pulse generator for generating at least two clocked pulse signals from a global clock signal is provided. The clock pulse generator includes at least one input for receiving a clock signal having a rising and a falling edge and a mechanism for selectably delaying a rising edge of a pulse signal synchronized to the falling edge of the clock signal. The clock pulse generator further includes a first selectable duration pulse synchronized to the rising edge of the clock signal and a second selectable duration pulse synchronized to the selectably delayed rising edge. The clock pulse generator also includes a glitch avoidance circuit to remove glitches in the clock signal before it is used.Type: GrantFiled: March 13, 2003Date of Patent: May 10, 2005Assignee: International Business Machines CorporationInventors: Hung Cai Ngo, Wendy Ann Belluomini, Robert Kevin Montoye
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Patent number: 6819141Abstract: A high speed static multiplexer comprising: (1) a plurality of data inputs and at least one select input; (2) an output; (3) a high voltage rail and a low voltage rail; (4) a pull-up circuit coupled between the output and the high voltage rail and further coupled to receive the data inputs and the select input so that the pull-up circuit generates a first logic state at the output in response to the selected data input having that first logic state; (5) and a pull-down circuit coupled between the output and the low voltage rail and further coupled to receive the data inputs and the select input, so that the pull-down circuit generates a second logic state at the output in response to the selected data input having that second logic state.Type: GrantFiled: March 14, 2000Date of Patent: November 16, 2004Assignee: International Business Machines CorporationInventors: Jieming Qi, Hung Cai Ngo
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Publication number: 20040178838Abstract: A clock pulse generator for generating at least two clocked pulse signals from a global clock signal is provided. The clock pulse generator includes at least one input for receiving a clock signal having a rising and a falling edge and a mechanism for selectably delaying a rising edge of a pulse signal synchronized to the falling edge of the clock signal. The clock pulse generator further includes a first selectable duration pulse synchronized to the rising edge of the clock signal and a second selectable duration pulse synchronized to the selectably delayed rising edge. The clock pulse generator also includes a glitch avoidance circuit to remove glitches in the clock signal before it is used.Type: ApplicationFiled: March 13, 2003Publication date: September 16, 2004Applicant: International Business Machines CorporationInventors: Hung Cai Ngo, Wendy Ann Belluomini, Robert Kevin Montoye
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Patent number: 6763474Abstract: An apparatus and a method for node synchronization that can be used in a heterogeneous computer system where nodes in the system do not share a common system clock. Time stamps, which are critically important, are attached to transaction requests. Time stamps are based on a “time of day” value, which may simply be a register incremented by a system clock. Since each node has its own system clock, the frequency of these clocks may drift which results in variation in the time stamp values. If the values drift too far apart, data updates may be lost. A frequency synthesizer capable of high resolution and rapid frequency adjustments can be connected to system clock. When a shift in phase between the master and slave time of day values is detected, the frequency synthesizer output can be changed by a small amount to bring the two signals back into phase.Type: GrantFiled: August 3, 2000Date of Patent: July 13, 2004Assignee: International Business Machines CorporationInventors: David William Boerstler, Mark Edward Dean, Hung Cai Ngo, Andrew Christian Zimmerman
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Patent number: 6710668Abstract: According to an apparatus form of the invention, oscillator circuitry for operating a number of inverters in a loop (also known as a “ring”) includes a number of inverters. The inverters include a series of M inverters and a series of N inverters. The M inverters have signal propagation delay of m and the N inverters have signal propagation delay of n. The circuitry also includes means for selecting whether to exclude the N inverters from operating in the loop operable for receiving a select signal on a data input. The selecting means times assertion of the select signal on an output to select the number of inverters. In order to glitchlessly change the number of inverters operating in the loop, the selecting means has a certain delay greater than delay n.Type: GrantFiled: September 12, 2002Date of Patent: March 23, 2004Assignee: International Business Machines CorporationInventors: Gary Dale Carpenter, Hung Cai Ngo, Ivan Vo
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Publication number: 20040051593Abstract: According to an apparatus form of the invention, oscillator circuitry for operating a number of inverters in a loop (also known as a “ring”) includes a number of inverters. The inverters include a series of M inverters and a series of N inverters. The M inverters have signal propagation delay of m and the N inverters have signal propagation delay of n. The circuitry also includes means for selecting whether to exclude the N inverters from operating in the loop operable for receiving a select signal on a data input. The selecting means times assertion of the select signal on an output to select the number of inverters. In order to glitchlessly change the number of inverters operating in the loop, the selecting means has a certain delay greater than delay n.Type: ApplicationFiled: September 12, 2002Publication date: March 18, 2004Applicant: International Business Machines CorporationInventors: Gary Dale Carpenter, Hung Cai Ngo, Ivan Vo
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Patent number: 6650145Abstract: Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a dynamic portion and a static portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock, permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element and, obviating a need for keeper device.Type: GrantFiled: April 4, 2002Date of Patent: November 18, 2003Assignee: International Business Machines CorporationInventors: Hung Cai Ngo, Wendy Ann Belluomini, Robert Kevin Montoye
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Publication number: 20030189445Abstract: Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a dynamic portion and a static portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock, permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element and, obviating a need for keeper device.Type: ApplicationFiled: April 4, 2002Publication date: October 9, 2003Applicant: International Business Machines CorporationInventors: Hung Cai Ngo, Wendy Ann Belluomini, Robert Kevin Montoye
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Patent number: 6566921Abstract: An apparatus and a method for making high resolution frequency adjustments in a multistage frequency synthesizer. The initial stage of the frequency synthesizer is a conventional phase lock loop connected to a dynamically variable frequency divider. There are one or more intermediate stages that consist of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to a dynamically variable frequency divider. The final stage consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to another fixed frequency divider. By varying the constant of division in the variable frequency dividers in the circuit, fine frequency adjustments can be made very rapidly. The precision of the adjustments depends on the relative values of the frequency dividers and the number of intermediate stages in the system.Type: GrantFiled: August 3, 2000Date of Patent: May 20, 2003Assignee: International Business Machines CorporationInventors: David William Boerstler, Mark Edward Dean, Hung Cai Ngo, Andrew Christian Zimmerman
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Patent number: 6529084Abstract: A voltage controlled oscillator (VCO) and phase-locked loop (PLL) topologies that allow for low-voltage, high frequency, low-jitter operation are disclosed. The conventional PLL design is modified so as to bifurcate the error signal into AC and DC components. A VCO accepting AC- and DC-component control inputs adjusts its output frequency in accordance with both inputs.Type: GrantFiled: October 11, 2001Date of Patent: March 4, 2003Assignee: International Business Machines CorporationInventors: David William Boerstler, Juan-Antonio Carballo, Gary Dale Carpenter, Hung Cai Ngo, Kevin John Nowka
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Patent number: 6522207Abstract: An apparatus and a method for making small frequency adjustments in a frequency synthesizer. The frequency synthesizer consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and the output of the forward portion of the phase locked loop connected to a dynamically variable frequency divider. By changing the constant of division in the variable frequency divider, the output of the frequency divider can be rapidly changed in small increments. The dynamically variable frequency divider is key to this design. This digital circuit stores the current divisor value and has an input for a new divisor value. When a signal is sent to switch to the new divisor value, the circuit uses an incrementer and associated logic to rapidly change to the new constant of division.Type: GrantFiled: August 3, 2000Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: David William Boerstler, Mark Edward Dean, Hung Cai Ngo, Andrew Christian Zimmerman