Patents by Inventor Hung Cai Ngo
Hung Cai Ngo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6501313Abstract: A method of controlling a clock signal in a clock distribution network, by detecting an error in a duty cycle of the clock signal, and dynamically adjusting the body voltage of one or more devices in the clock distribution network, based on the detected error. Where the electronic device is a p-type device, the adjustment may be performed by reducing the body voltage of the p-type device with respect to a supply voltage. Where the electronic device is an n-type device, the adjustment may be performed by increasing the body voltage of the n-type device with respect to a reference plane. The invention may be implemented digitally, that is, with the body voltage of the electronic device being adjusted by selectively connecting a body contact of the device to one of several discrete voltages using a multiplexer.Type: GrantFiled: December 27, 2000Date of Patent: December 31, 2002Assignee: International Business Machines CorporationInventors: David William Boerstler, Daniel Mark Dreps, Byron Lee Krauter, Hung Cai Ngo
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Publication number: 20020079940Abstract: A method of controlling a clock signal in a clock distribution network, by detecting an error in a duty cycle of the clock signal, and dynamically adjusting the body voltage of one or more devices in the clock distribution network, based on the detected error. Where the electronic device is a p-type device, the adjustment may be performed by reducing the body voltage of the p-type device with respect to a supply voltage. Where the electronic device is an n-type device, the adjustment may be performed by increasing the body voltage of the n-type device with respect to a reference plane. The invention may be implemented digitally, that is, with the body voltage of the electronic device being adjusted by selectively connecting a body contact of the device to one of several discrete voltages using a multiplexer.Type: ApplicationFiled: December 27, 2000Publication date: June 27, 2002Applicant: International Business Machines CorporationInventors: David William Boerstler, Daniel Mark Dreps, Byron Lee Krauter, Hung Cai Ngo
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Patent number: 6407574Abstract: Disclosed is a system for reducing propagation delays caused by capacitive coupling of RC interconnects. The system comprises a first interconnect utilized for propagating signals, a second interconnect also utilized for propagating signals but which propagates signals at a faster rate than the first interconnect, and a charge dumping circuit with an input coupled to a point on the second interconnect and an output coupled to a corresponding point on the first interconnect. The charge dumping circuit includes a pulse generation circuit and a select-signal generation circuit, both of which are utilized to enable charge to be dumped from the second interconnect to the first interconnect to increase switching times of the signals propagating on the first interconnect and improve overall propagation speed.Type: GrantFiled: September 26, 2000Date of Patent: June 18, 2002Assignee: International Business Machines CorporationInventors: Huajun Wen, Hung Cai Ngo
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Patent number: 6404235Abstract: A dynamic circuit having reduced dynamic node switching latency. The operating status of the dynamic circuit alternates between a pre-charge phase in which a pre-charge device charges the dynamic node, and an evaluation phase in which data at the input of the dynamic circuit may or may not precipitate a dynamic node discharge. Each evaluation phase may be characterized as including an initial standby interval prior to the evaluation discharge, followed by an evaluate interval over which the dynamic node completes an evaluation discharge. A standby device is utilized to drive an output of the dynamic circuit low during a pre-charge phase and to maintain the output low during an standby interval in which dynamic circuit inputs do not result in the dynamic node being discharged. The dynamic circuit includes a standby control circuit that disables the standby device during the evaluation interval, resulting in reduced dynamic node switching capacitance.Type: GrantFiled: August 31, 2000Date of Patent: June 11, 2002Assignee: International Business Machines CorporationInventors: Kevin J. Nowka, Hung Cai Ngo, Jieming Qi
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Patent number: 6393446Abstract: A dual mode rotator capable of performing 32-bit and 64-bit rotation. According to a preferred embodiment, the dual mode rotator includes a first, second, and third rotator units wherein each rotator has a plurality of inputs and outputs. The inputs of the second rotator are operatively connected to the corresponding outputs of the first rotator unit. The inputs of the third rotator unit are operatively connected to the corresponding outputs of the second rotator. Responsive to selection of 32-bit rotation mode, the upper half of the inputs to the first rotator are zero and the lower half of the outputs of the third rotator are replicated in the upper half of the outputs of the third rotator.Type: GrantFiled: June 30, 1999Date of Patent: May 21, 2002Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Hung Cai Ngo, Jaehong Park, Joel Abraham Silberman
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Patent number: 6360238Abstract: A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.Type: GrantFiled: March 15, 1999Date of Patent: March 19, 2002Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Kyung Tek Lee, Hung Cai Ngo, Kevin John Nowka
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Patent number: 6345286Abstract: A 6-to-3 carry-save binary adder is disclosed. The 6-to-3 carry-save adder includes a means for receiving six data inputs and a means for simultaneously adding the six data inputs to generate a first data output, a second data output, and a third data output. The first data output is a SUM output, the second data output is a CARRY—2 output, and the third data output is a CARRY—4 output.Type: GrantFiled: October 30, 1998Date of Patent: February 5, 2002Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Hung Cai Ngo, Kevin John Nowka
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Patent number: 6335650Abstract: A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.Type: GrantFiled: September 28, 2000Date of Patent: January 1, 2002Assignee: International Business Machines CorporationInventors: David William Boerstler, Harm Peter Hofstee, Hung Cai Ngo, Kevin John Nowka
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Patent number: 6335900Abstract: A method and apparatus for selectable word line boosting in a memory device provides operating of the memory device over wide power supply ranges. A voltage reference and a comparator determine whether or not the power supply voltage has dropped below the range in which word line boosting is not required. If the power supply voltage has dropped, word line boosting is enabled, improving the noise margin and access time of the memory when operating at lower voltages.Type: GrantFiled: December 12, 2000Date of Patent: January 1, 2002Assignee: International Business Machines CorporationInventors: Ohsang Kwon, Hung Cai Ngo, Kevin John Nowka
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Patent number: 6292027Abstract: Fast low-power logic gates and method for evaluating logic signals reduce the effect of the power/speed tradeoff for parallel connected logic. A control circuit momentarily enables a high-current pullup or pulldown device after a connected input ladder switches from a conducting state to a non-conducting state. This allows a high current pullup or pulldown to be used for fast evaluation without increasing overall current drain, since the pullup action is momentary.Type: GrantFiled: November 16, 1999Date of Patent: September 18, 2001Assignee: International Business Machines CorporationInventors: Sand Hoo Dhong, Hung Cai Ngo, Jaehong Park, Osamu Takahashi
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Patent number: 6285218Abstract: A method and apparatus for implementing dynamic logic with programmable dynamic logic gates acts as a complement to programmable logic arrays (PLAs) used in high-speed microprocessor designs. A matrix of selectable cells provides powerful logic functions such as AND-OR gate capability with a minimum of inputs and transistors. By using programmable logic arrays and programmable dynamic gates, the efficiency of a logic block can be dramatically improved with little added circuit area.Type: GrantFiled: May 10, 2000Date of Patent: September 4, 2001Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Hung Cai Ngo, Jaehong Park, Osamu Takahashi
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Patent number: 6282557Abstract: A low latency fused multiply-adder for adding a product of a first binary number and a second binary number to a third binary number is disclosed. The low latency fused multiply-adder includes a partial product generation module, a partial product reduction module, and a carry propagate adder. The partial product generation module generates a set of partial products from the first binary number and the second binary number. Coupled to the partial product generation module, the partial product reduction module combines the set of partial products with the third binary number to produce a redundant Sum and a redundant Carry. Finally, the carry propagate adder adds the redundant Sum and the redundant Carry to yield a Sum Total.Type: GrantFiled: December 8, 1998Date of Patent: August 28, 2001Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Hung Cai Ngo, Kevin John Nowka
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Patent number: 6232872Abstract: A 64-bit comparator includes a first stage for receiving a 64-bit number A and a 64-bit number B, and generating first output values. A second stage then receives the first output values from the first stage and outputs second output values, and a third stage receives the second output values from the second stage and outputs greater than, less than, and equivalent values. Thus, the comparator is faster in that it is implemented in three logic stages by making efficient use of compound dynamic gates.Type: GrantFiled: October 14, 1999Date of Patent: May 15, 2001Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Hung Cai Ngo, Jaehong Park
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Patent number: 6178437Abstract: A method for anticipating leading zeros/ones in a floating-point processor is disclosed. A leading zeros string and a leading ones string is generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is calculated directly and concurrently from the leading zeros string and the leading ones strings prior to a determination of a sign of an output of the positive sum and the negative sum.Type: GrantFiled: August 25, 1998Date of Patent: January 23, 2001Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Hung Cai Ngo, Kevin John Nowka
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Patent number: 6175852Abstract: A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple eight-bit group generate circuits and multiple eight-bit group propagate circuits. Each of the eight-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the eight-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.Type: GrantFiled: July 13, 1998Date of Patent: January 16, 2001Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Hung Cai Ngo, Kevin John Nowka
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Patent number: 5964827Abstract: A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple four-bit group generate circuits and multiple four-bit group propagate circuits. Each of the four-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the four-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.Type: GrantFiled: November 17, 1997Date of Patent: October 12, 1999Assignee: International Business Machines CorporationInventors: Hung Cai Ngo, Sang Hoo Dhong, Joel Abraham Silberman
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Patent number: 5757682Abstract: A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing.Type: GrantFiled: March 31, 1995Date of Patent: May 26, 1998Assignee: International Business Machines CorporationInventors: Eric Mark Schwarz, Robert Michael Bunce, Leon Jacob Sigal, Hung Cai Ngo
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Patent number: 5742536Abstract: A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing.Type: GrantFiled: June 7, 1995Date of Patent: April 21, 1998Assignee: International Business Machines CorporationInventors: Eric Mark Schwarz, Robert Michael Bunce, Leon Jacob Sigal, Hung Cai Ngo
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Patent number: 5742535Abstract: A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing.Type: GrantFiled: June 5, 1995Date of Patent: April 21, 1998Assignee: International Business Machines CorporationInventors: Eric Mark Schwarz, Robert Michael Bunce, Leon Jacob Sigal, Hung Cai Ngo