Patents by Inventor Hung-Chang Hsieh
Hung-Chang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11735477Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.Type: GrantFiled: May 21, 2020Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Feng Shieh, Hung-Chang Hsieh, Wen-Hung Tseng
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Patent number: 11378894Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.Type: GrantFiled: October 28, 2019Date of Patent: July 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shang-Chieh Chien, Jeng-Horng Chen, Jui-Ching Wu, Chia-Chen Chen, Hung-Chang Hsieh, Chi-Lun Lu, Chia-Hao Yu, Shih-Ming Chang, Anthony Yen
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Patent number: 11081394Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.Type: GrantFiled: October 8, 2018Date of Patent: August 3, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Feng Shieh, Wen-Hung Tseng, Tzung-Hua Lin, Hung-Chang Hsieh
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Publication number: 20200286782Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.Type: ApplicationFiled: May 21, 2020Publication date: September 10, 2020Inventors: Ming-Feng Shieh, Hung-Chang Hsieh, Wen-Hung Tseng
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Patent number: 10672656Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.Type: GrantFiled: October 5, 2015Date of Patent: June 2, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Feng Shieh, Hung-Chang Hsieh, Wen-Hung Tseng
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Publication number: 20200064747Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.Type: ApplicationFiled: October 28, 2019Publication date: February 27, 2020Inventors: Shang-Chieh Chien, Jeng-Horng Chen, Jui-Ching Wu, Chia-Chen Chen, Hung-Chang Hsieh, Chi-Lun Lu, Chia-Hao Yu, Shih-Ming Chang, Anthony Yen
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Patent number: 10522413Abstract: Methods are disclosed herein for fabricating semiconductor devices having shared source/drain contacts. An exemplary semiconductor device includes a high-k/metal gate stack disposed over a substrate. The high-k/metal gate stack is disposed between a first source/drain feature and a second source/drain feature. A first spacer set is disposed along sidewalls of the high-k/metal gate stack. A first interlevel dielectric (ILD) layer is disposed over the substrate. Upper portions of the first spacer set that extend above the first ILD layer have a tapered width. A second spacer set is disposed on the upper portions of the first spacer set and over the first ILD layer. A second ILD layer is disposed over the first ILD layer. A contact feature extends through the second ILD layer to the first source/drain feature and the second source/drain feature. The contact feature spans uninterrupted between the first source/drain feature and the second source/drain feature.Type: GrantFiled: December 21, 2018Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
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Patent number: 10459353Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.Type: GrantFiled: January 30, 2014Date of Patent: October 29, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Chieh Chien, Jeng-Horng Chen, Jui-Ching Wu, Chia-Chen Chen, Hung-Chang Hsieh, Chi-Lun Lu, Chia-Hao Yu, Shih-Ming Chang, Anthony Yen
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Publication number: 20190115262Abstract: Methods are disclosed herein for fabricating semiconductor devices having shared source/drain contacts. An exemplary semiconductor device includes a high-k/metal gate stack disposed over a substrate. The high-k/metal gate stack is disposed between a first source/drain feature and a second source/drain feature. A first spacer set is disposed along sidewalls of the high-k/metal gate stack. A first interlevel dielectric (ILD) layer is disposed over the substrate. Upper portions of the first spacer set that extend above the first ILD layer have a tapered width. A second spacer set is disposed on the upper portions of the first spacer set and over the first ILD layer. A second ILD layer is disposed over the first ILD layer. A contact feature extends through the second ILD layer to the first source/drain feature and the second source/drain feature. The contact feature spans uninterrupted between the first source/drain feature and the second source/drain feature.Type: ApplicationFiled: December 21, 2018Publication date: April 18, 2019Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
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Publication number: 20190051564Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.Type: ApplicationFiled: October 8, 2018Publication date: February 14, 2019Inventors: Ming-Feng Shieh, Wen-Hung Tseng, Tzung-Hua Lin, Hung-Chang Hsieh
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Patent number: 10163720Abstract: Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is disposed over a substrate and between source/drain features. A first dielectric layer is formed over the substrate and recessed to expose upper portions of the first spacers. A spacer layer is then formed over the upper portions of the first spacers. A second dielectric layer is formed over the spacer layer, and a patterned masking layer is formed over the second dielectric layer. The second dielectric layer, the spacer layer, and the first dielectric layer are patterned. For example, exposed portions of the second dielectric layer, the spacer layer (forming second spacers disposed along the upper portions of the first spacers), and the first dielectric layer are etched to form a trench exposing the gate structure and the source/drain features. The trench is filled with a conductive material.Type: GrantFiled: October 23, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
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Patent number: 10101659Abstract: A lithography method is provided in accordance with some embodiments. The lithography method includes forming a surface modification layer on a substrate, the surface modification layer including a hydrophilic top surface; coating a photoresist layer on the surface modification layer; and developing the photoresist layer, thereby forming a patterned photoresist layer.Type: GrantFiled: November 18, 2016Date of Patent: October 16, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Shu-Fang Chen, Hung-Chung Chien, Lin-Hung Shiu, Hung-Chang Hsieh
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Patent number: 10096519Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.Type: GrantFiled: September 6, 2016Date of Patent: October 9, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Feng Shieh, Wen-Hung Tseng, Tzung-Hua Lin, Hung-Chang Hsieh
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Patent number: 9996011Abstract: A method provides an integrated circuit (IC) substrate having first and second alignment marks defined in a first pattern layer, and third and fourth alignment marks defined in a second pattern layer. The first and second alignment marks are illuminated, through a photomask, with a first light to determine a first layer alignment error including a first alignment error and a second alignment error. The first alignment error has more weight than the second alignment error in determining the first layer alignment error. The third and fourth alignment marks are illuminated with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to the fourth alignment mark. The third alignment error has more weight than the fourth alignment error in determining the second layer alignment error.Type: GrantFiled: April 4, 2016Date of Patent: June 12, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hsien Lin, Hung-Chang Hsieh, Feng-Jia Shiu, Chun-Yi Lee
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Patent number: 9929153Abstract: A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming a mandrel features over a substrate, the mandrel feature and performing a coarse cut to remove one or more mandrel features to form a coarse space. After the coarse cut, the substrate is etched by using the mandrel features, with the coarse space as an etch mask, to form fins. A spacer layer is deposited to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the coarse space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the coarse space. A fine cut is performed to remove a portion of one or more mandrel features to form an end-to-end space. An isolation trench is formed in the end-to-end space and the coarse space.Type: GrantFiled: October 18, 2013Date of Patent: March 27, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Weng-Hung Tseng, Tzung-Hua Lin, Hung-Chang Hsieh
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Publication number: 20180061715Abstract: Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is disposed over a substrate and between source/drain features. A first dielectric layer is formed over the substrate and recessed to expose upper portions of the first spacers. A spacer layer is then formed over the upper portions of the first spacers. A second dielectric layer is formed over the spacer layer, and a patterned masking layer is formed over the second dielectric layer. The second dielectric layer, the spacer layer, and the first dielectric layer are patterned. For example, exposed portions of the second dielectric layer, the spacer layer (forming second spacers disposed along the upper portions of the first spacers), and the first dielectric layer are etched to form a trench exposing the gate structure and the source/drain features. The trench is filled with a conductive material.Type: ApplicationFiled: October 23, 2017Publication date: March 1, 2018Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
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Patent number: 9905471Abstract: A method includes depositing an ESL on a substrate; patterning the ESL such that a first region of the substrate is covered thereby and a second region of the substrate is exposed within an opening of the etch stop layer; depositing a first dielectric layer on the ESL in the first region and on the substrate in the second region; patterning the first dielectric layer to form a first trench through the first dielectric layer in the first region; forming a metal feature in the first trench; depositing a second dielectric layer over the metal feature in the first region and over the first dielectric layer in the second region; and performing a patterning process to form a second trench through the second dielectric layer in the first region, and to form a third trench through the second and first dielectric layers in the second region.Type: GrantFiled: February 16, 2017Date of Patent: February 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yuan-Yen Lo, Jhih-Yu Wang, Jhun Hua Chen, Hung-Chang Hsieh
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Publication number: 20180047561Abstract: A lithography method is provided in accordance with some embodiments. The lithography method includes forming a surface modification layer on a substrate, the surface modification layer including a hydrophilic top surface; coating a photoresist layer on the surface modification layer; and developing the photoresist layer, thereby forming a patterned photoresist layer.Type: ApplicationFiled: November 18, 2016Publication date: February 15, 2018Inventors: Shu-Fang Chen, Hung-Chung Chien, Lin-Hung Shiu, Hung-Chang Hsieh
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Patent number: 9875892Abstract: A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material.Type: GrantFiled: May 8, 2015Date of Patent: January 23, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Wei Chang, Chih-Chien Wang, Wang-Pen Mo, Hung-Chang Hsieh
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Patent number: 9823574Abstract: A device for semiconductor fabrication includes a substrate and a layer formed over the substrate, wherein the layer includes an alignment mark. The alignment mark includes a first plurality of elongated members that are oriented lengthwise along a first direction and are distributed along a second direction. The alignment mark further includes a second plurality of elongated members that are oriented lengthwise along a third direction perpendicular to the first direction and are distributed along the second direction, wherein the second direction is different from each of the first and third directions.Type: GrantFiled: September 29, 2015Date of Patent: November 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Huang Chen, Hung-Chang Hsieh, Kuei-Liang Lu, Ya Hui Chang, Spencer Lin