Patents by Inventor Hung-Chang Hsieh

Hung-Chang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200286782
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Inventors: Ming-Feng Shieh, Hung-Chang Hsieh, Wen-Hung Tseng
  • Patent number: 10672656
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Feng Shieh, Hung-Chang Hsieh, Wen-Hung Tseng
  • Publication number: 20200064747
    Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 27, 2020
    Inventors: Shang-Chieh Chien, Jeng-Horng Chen, Jui-Ching Wu, Chia-Chen Chen, Hung-Chang Hsieh, Chi-Lun Lu, Chia-Hao Yu, Shih-Ming Chang, Anthony Yen
  • Patent number: 10522413
    Abstract: Methods are disclosed herein for fabricating semiconductor devices having shared source/drain contacts. An exemplary semiconductor device includes a high-k/metal gate stack disposed over a substrate. The high-k/metal gate stack is disposed between a first source/drain feature and a second source/drain feature. A first spacer set is disposed along sidewalls of the high-k/metal gate stack. A first interlevel dielectric (ILD) layer is disposed over the substrate. Upper portions of the first spacer set that extend above the first ILD layer have a tapered width. A second spacer set is disposed on the upper portions of the first spacer set and over the first ILD layer. A second ILD layer is disposed over the first ILD layer. A contact feature extends through the second ILD layer to the first source/drain feature and the second source/drain feature. The contact feature spans uninterrupted between the first source/drain feature and the second source/drain feature.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
  • Patent number: 10459353
    Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Chieh Chien, Jeng-Horng Chen, Jui-Ching Wu, Chia-Chen Chen, Hung-Chang Hsieh, Chi-Lun Lu, Chia-Hao Yu, Shih-Ming Chang, Anthony Yen
  • Publication number: 20190326469
    Abstract: A light-emitting device and a manufacturing method thereof are provided. The light-emitting device includes a substrate, an epitaxial blocking layer, and a light-emitting epitaxial structure. The substrate has a surface, in which the surface includes a plurality of protruding parts and a plurality of recess parts relative to the protruding parts. The epitaxial blocking layer disposed on the substrate covers the recess parts and exposes the protruding parts. The light-emitting epitaxial structure disposed on the substrate is connected to the protruding parts and is disposed above the recess parts. The light-emitting epitaxial structure is formed by using the protruding parts as a growth surface thereof so as to have a better crystalline quality.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Inventors: HUNG-CHIH YANG, XIAO-KUN LIN, JIAN-RAN HUANG, BEN-JIE FAN, HO-CHIEN CHEN, CHAN-YANG LU, SHUEN-TA TENG, CHENG-CHANG HSIEH
  • Publication number: 20190115262
    Abstract: Methods are disclosed herein for fabricating semiconductor devices having shared source/drain contacts. An exemplary semiconductor device includes a high-k/metal gate stack disposed over a substrate. The high-k/metal gate stack is disposed between a first source/drain feature and a second source/drain feature. A first spacer set is disposed along sidewalls of the high-k/metal gate stack. A first interlevel dielectric (ILD) layer is disposed over the substrate. Upper portions of the first spacer set that extend above the first ILD layer have a tapered width. A second spacer set is disposed on the upper portions of the first spacer set and over the first ILD layer. A second ILD layer is disposed over the first ILD layer. A contact feature extends through the second ILD layer to the first source/drain feature and the second source/drain feature. The contact feature spans uninterrupted between the first source/drain feature and the second source/drain feature.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 18, 2019
    Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
  • Publication number: 20190051564
    Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 14, 2019
    Inventors: Ming-Feng Shieh, Wen-Hung Tseng, Tzung-Hua Lin, Hung-Chang Hsieh
  • Patent number: 10163720
    Abstract: Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is disposed over a substrate and between source/drain features. A first dielectric layer is formed over the substrate and recessed to expose upper portions of the first spacers. A spacer layer is then formed over the upper portions of the first spacers. A second dielectric layer is formed over the spacer layer, and a patterned masking layer is formed over the second dielectric layer. The second dielectric layer, the spacer layer, and the first dielectric layer are patterned. For example, exposed portions of the second dielectric layer, the spacer layer (forming second spacers disposed along the upper portions of the first spacers), and the first dielectric layer are etched to form a trench exposing the gate structure and the source/drain features. The trench is filled with a conductive material.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
  • Patent number: 10101659
    Abstract: A lithography method is provided in accordance with some embodiments. The lithography method includes forming a surface modification layer on a substrate, the surface modification layer including a hydrophilic top surface; coating a photoresist layer on the surface modification layer; and developing the photoresist layer, thereby forming a patterned photoresist layer.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shu-Fang Chen, Hung-Chung Chien, Lin-Hung Shiu, Hung-Chang Hsieh
  • Patent number: 10096519
    Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Feng Shieh, Wen-Hung Tseng, Tzung-Hua Lin, Hung-Chang Hsieh
  • Patent number: 9996011
    Abstract: A method provides an integrated circuit (IC) substrate having first and second alignment marks defined in a first pattern layer, and third and fourth alignment marks defined in a second pattern layer. The first and second alignment marks are illuminated, through a photomask, with a first light to determine a first layer alignment error including a first alignment error and a second alignment error. The first alignment error has more weight than the second alignment error in determining the first layer alignment error. The third and fourth alignment marks are illuminated with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to the fourth alignment mark. The third alignment error has more weight than the fourth alignment error in determining the second layer alignment error.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsien Lin, Hung-Chang Hsieh, Feng-Jia Shiu, Chun-Yi Lee
  • Patent number: 9929153
    Abstract: A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming a mandrel features over a substrate, the mandrel feature and performing a coarse cut to remove one or more mandrel features to form a coarse space. After the coarse cut, the substrate is etched by using the mandrel features, with the coarse space as an etch mask, to form fins. A spacer layer is deposited to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the coarse space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the coarse space. A fine cut is performed to remove a portion of one or more mandrel features to form an end-to-end space. An isolation trench is formed in the end-to-end space and the coarse space.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Weng-Hung Tseng, Tzung-Hua Lin, Hung-Chang Hsieh
  • Publication number: 20180061715
    Abstract: Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is disposed over a substrate and between source/drain features. A first dielectric layer is formed over the substrate and recessed to expose upper portions of the first spacers. A spacer layer is then formed over the upper portions of the first spacers. A second dielectric layer is formed over the spacer layer, and a patterned masking layer is formed over the second dielectric layer. The second dielectric layer, the spacer layer, and the first dielectric layer are patterned. For example, exposed portions of the second dielectric layer, the spacer layer (forming second spacers disposed along the upper portions of the first spacers), and the first dielectric layer are etched to form a trench exposing the gate structure and the source/drain features. The trench is filled with a conductive material.
    Type: Application
    Filed: October 23, 2017
    Publication date: March 1, 2018
    Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
  • Patent number: 9905471
    Abstract: A method includes depositing an ESL on a substrate; patterning the ESL such that a first region of the substrate is covered thereby and a second region of the substrate is exposed within an opening of the etch stop layer; depositing a first dielectric layer on the ESL in the first region and on the substrate in the second region; patterning the first dielectric layer to form a first trench through the first dielectric layer in the first region; forming a metal feature in the first trench; depositing a second dielectric layer over the metal feature in the first region and over the first dielectric layer in the second region; and performing a patterning process to form a second trench through the second dielectric layer in the first region, and to form a third trench through the second and first dielectric layers in the second region.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: February 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuan-Yen Lo, Jhih-Yu Wang, Jhun Hua Chen, Hung-Chang Hsieh
  • Publication number: 20180047561
    Abstract: A lithography method is provided in accordance with some embodiments. The lithography method includes forming a surface modification layer on a substrate, the surface modification layer including a hydrophilic top surface; coating a photoresist layer on the surface modification layer; and developing the photoresist layer, thereby forming a patterned photoresist layer.
    Type: Application
    Filed: November 18, 2016
    Publication date: February 15, 2018
    Inventors: Shu-Fang Chen, Hung-Chung Chien, Lin-Hung Shiu, Hung-Chang Hsieh
  • Patent number: 9875892
    Abstract: A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Wei Chang, Chih-Chien Wang, Wang-Pen Mo, Hung-Chang Hsieh
  • Patent number: 9823574
    Abstract: A device for semiconductor fabrication includes a substrate and a layer formed over the substrate, wherein the layer includes an alignment mark. The alignment mark includes a first plurality of elongated members that are oriented lengthwise along a first direction and are distributed along a second direction. The alignment mark further includes a second plurality of elongated members that are oriented lengthwise along a third direction perpendicular to the first direction and are distributed along the second direction, wherein the second direction is different from each of the first and third directions.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Huang Chen, Hung-Chang Hsieh, Kuei-Liang Lu, Ya Hui Chang, Spencer Lin
  • Publication number: 20170316983
    Abstract: A method includes depositing an ESL on a substrate; patterning the ESL such that a first region of the substrate is covered thereby and a second region of the substrate is exposed within an opening of the etch stop layer; depositing a first dielectric layer on the ESL in the first region and on the substrate in the second region; patterning the first dielectric layer to form a first trench through the first dielectric layer in the first region; forming a metal feature in the first trench; depositing a second dielectric layer over the metal feature in the first region and over the first dielectric layer in the second region; and performing a patterning process to form a second trench through the second dielectric layer in the first region, and to form a third trench through the second and first dielectric layers in the second region.
    Type: Application
    Filed: February 16, 2017
    Publication date: November 2, 2017
    Inventors: Yuan-Yen Lo, Jhih-Yu Wang, Jhun Hua Chen, Hung-Chang Hsieh
  • Patent number: 9805154
    Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and inserting a first plurality of scattering bars in the IC design layout to form a first circular pattern of scattering bars around the first main feature. The first main feature is positioned at a center portion of the first circular pattern of scattering bars.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Irene Ho, Ai-Jen Hung, Hung-Chang Hsieh, Kuei-Liang Lu, Ya Hui Chang