Patents by Inventor Hung Chang Yu
Hung Chang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901030Abstract: A memory device includes a memory array, a reference voltage generator and a driver circuit. The memory array includes a memory cell. The reference voltage generator is configured to generate a reference voltage based on a threshold voltage of a select transistor of the memory cell. The driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage, and the reference voltage generator comprises a resistor that is configured to sense the threshold voltage of the select transistor through a current flowing through the resistor.Type: GrantFiled: June 24, 2022Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hung-Chang Yu
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Publication number: 20230380184Abstract: A method includes: providing a modulation circuit including a first resistive element, a second resistive element and a third resistive element; providing a memory array and a regulator connecting the modulation circuit to the memory array, wherein the regulator includes a transistor; determining an operation mode of the memory array; generating a first voltage at a drain terminal of the transistor, wherein the first voltage corresponds to a positive, negative zero temperature coefficient according to a first resistance ratio and a second resistance ratio; during a read operation, providing a first driving current to the memory array in response to the first voltage corresponding to the positive temperature coefficient; and during a write operation, providing a second driving current to the memory array in response to the first voltage corresponding to the negative temperature coefficient.Type: ApplicationFiled: July 30, 2023Publication date: November 23, 2023Inventor: HUNG-CHANG YU
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Publication number: 20230380185Abstract: A method includes: providing a modulation circuit and a driving circuit, the modulation circuit configured to generate a temperature-dependent voltage and provide the same to the driving circuit; determined an operation mode of a memory array; providing a first current corresponding to a positive temperature coefficient by the driving circuit in response to the operation mode being a read operation on the memory array; and providing a second current corresponding to a negative temperature coefficient by the driving circuit in response to the operation mode being a write operation on the memory array.Type: ApplicationFiled: August 8, 2023Publication date: November 23, 2023Inventor: HUNG-CHANG YU
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Patent number: 11793000Abstract: A method includes: providing a modulation circuit, determined an operation mode of a memory array, providing a first voltage corresponding to a positive temperature coefficient in response to a read operation of the memory array, and providing a second voltage corresponding to a negative temperature coefficient in response to a write operation of the memory array. The modulation circuit is configured to generate a temperature-dependent voltage and provide the same to the memory array.Type: GrantFiled: March 14, 2021Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Hung-Chang Yu
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Publication number: 20230178120Abstract: A method (for recycling charge from a first bit line of a memory device to a second bit line of the memory device) includes: before pre-filling the second bit line, momentarily closing switches to transfer a first charge from the first bit line which is involved in a first read operation to the second bit line which is involved subsequently in a second read operation; and each of the first bit line and the second bit line being served by a same sense amplifier.Type: ApplicationFiled: February 7, 2023Publication date: June 8, 2023Inventors: Hung-Chang YU, Ta-Ching YEH
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Publication number: 20230086858Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.Type: ApplicationFiled: November 28, 2022Publication date: March 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Hung-Chang Yu
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Patent number: 11574658Abstract: A semiconductor device includes: a sense amplifier; a branched line selectively connectable to the amplifier; an array of bit lines connected to corresponding memory cells; and an intra-sense-amplifier recycling arrangement configured to do as follows including: recovering a first charge from a first bit line associated with a first one of the memory cells, the first charge being associated with a preceding first evaluation performed by the sense amplifier; and boosting the branched line to a reference voltage including reusing the first charge to at least partially charge the branched line; and wherein the sense amplifier is configured to make a second evaluation of a stored value in a second memory cell relative to the reference voltage.Type: GrantFiled: June 8, 2021Date of Patent: February 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chang Yu, Ta-Ching Yeh
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Patent number: 11532341Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.Type: GrantFiled: April 29, 2021Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Hung-Chang Yu
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Publication number: 20220328124Abstract: A memory device includes a memory array, a reference voltage generator and a driver circuit. The memory array includes a memory cell. The reference voltage generator is configured to generate a reference voltage based on a threshold voltage of a select transistor of the memory cell. The driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage, and the reference voltage generator comprises a resistor that is configured to sense the threshold voltage of the select transistor through a current flowing through the resistor.Type: ApplicationFiled: June 24, 2022Publication date: October 13, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hung-Chang Yu
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Patent number: 11404140Abstract: A memory device includes a memory array, a reference voltage generator and a driver circuit. The memory array includes a memory cell for a memory operation. The reference voltage generator is configured to generate a reference voltage based on at least one of a temperature of the memory array or a threshold voltage of a select transistor of the memory cell. The driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage.Type: GrantFiled: January 4, 2021Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hung-Chang Yu
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Publication number: 20220215897Abstract: A memory device includes a memory array, a reference voltage generator and a driver circuit. The memory array includes a memory cell for a memory operation. The reference voltage generator is configured to generate a reference voltage based on at least one of a temperature of the memory array or a threshold voltage of a select transistor of the memory cell. The driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage.Type: ApplicationFiled: January 4, 2021Publication date: July 7, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hung-Chang Yu
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Publication number: 20210295881Abstract: A semiconductor device includes: a sense amplifier; a branched line selectively connectable to the amplifier; an array of bit lines connected to corresponding memory cells; and an intra-sense-amplifier recycling arrangement configured to do as follows including: recovering a first charge from a first bit line associated with a first one of the memory cells, the first charge being associated with a preceding first evaluation performed by the sense amplifier; and boosting the branched line to a reference voltage including reusing the first charge to at least partially charge the branched line; and wherein the sense amplifier is configured to make a second evaluation of a stored value in a second memory cell relative to the reference voltage.Type: ApplicationFiled: June 8, 2021Publication date: September 23, 2021Inventors: Hung-Chang YU, Ta-Ching YEH
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Publication number: 20210249062Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.Type: ApplicationFiled: April 29, 2021Publication date: August 12, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Hung-Chang Yu
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Publication number: 20210202575Abstract: A method includes: providing a modulation circuit, determined an operation mode of a memory array, providing a first voltage corresponding to a positive temperature coefficient in response to a read operation of the memory array, and providing a second voltage corresponding to a negative temperature coefficient in response to a write operation of the memory array. The modulation circuit is configured to generate a temperature-dependent voltage and provide the same to the memory array.Type: ApplicationFiled: March 14, 2021Publication date: July 1, 2021Inventor: HUNG-CHANG YU
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Patent number: 11031051Abstract: A semiconductor device includes: a sense amplifier; a branched line selectively connectable to the sense amplifier; a recycling arrangement selectively connectable to the branched line; an array of memory cells; an array of bit lines connected to corresponding memory cells in the array of memory cells; a multiplexer configured to selectively connect the branched line to a selected one in the array of memory cells through a corresponding line amongst the array of bit lines; and a controller configured to control the recycling arrangement and the multiplexer to perform intra-sense-amplifier recycling of a gleaned amount of charge (gleaned charge) recovered from a first read operation to a second read operation.Type: GrantFiled: November 27, 2019Date of Patent: June 8, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chang Yu, Ta-Ching Yeh
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Patent number: 11024395Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.Type: GrantFiled: June 29, 2018Date of Patent: June 1, 2021Inventors: Yu-Der Chih, Hung-Chang Yu, Ku-Feng Lin
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Patent number: 10998058Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.Type: GrantFiled: January 7, 2020Date of Patent: May 4, 2021Inventors: Yu-Der Chih, Hung-Chang Yu, Ku-Feng Lin
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Patent number: 10998024Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.Type: GrantFiled: March 2, 2020Date of Patent: May 4, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Hung-Chang Yu
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Patent number: 10950658Abstract: A circuit includes: a first node to receive a first current; a first resistive element receiving a first branch current of the first current; first transistors each including a first terminal connected to the second end of the first resistive element; a second resistive element connected to the first node and receiving a second branch current of the first current; a second node to receive a second current; a second transistor including a first terminal, the first terminal of the second transistor connected to the second node and receiving a first branch current of the second current; a third resistive element connected to the second node and receiving a second branch current of the second current; wherein a temperature coefficient is adjusted by a resistance of the second resistive element and a resistance of the third resistive element and corresponding to the first current.Type: GrantFiled: January 11, 2019Date of Patent: March 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Hung-Chang Yu
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Publication number: 20210035621Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.Type: ApplicationFiled: March 2, 2020Publication date: February 4, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Chin Lin, Hung-Chang Yu