Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

Abstract: A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A fist inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.

Abstract: A novel semiconductor device structure includes a first-conductivity-type semiconductor substrate, an isolated region, a first-conductivity-type MOS region, and a second-conductivity-type MOS region. A first-conductivity-type MOS transistor locates in the first-conductivity-type MOS region with a second-conductivity-type well surrounding, and a first-conductivity-type deep well surrounding the second-conductivity-type well with a second-conductivity-type deep well surrounding. In the second-conductivity-type MOS region, a second-conductivity-type MOS transistor is formed with a first-conductivity-type well surrounding. The first-conductivity-type deep well and the second-conductivity-type deep well are sufficiently reducing the noise and current leakage from other devices or from the semiconductor substrate.

Abstract: A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a semiconductor substrate, at least one deep n-well in the semiconductor substrate, at least one p-channel metal-oxide-semiconductor transistor in the deep n-well, at least one n-channel metal-oxide-semiconductor transistor outside of the deep n-well, an first interconnect structure, and a protection component. Both of the p-channel metal-oxide-semiconductor transistor and the n-channel metal-oxide-semiconductor transistor are disposed in the semiconductor substrate, and are electrically coupled by the first interconnect structure. The protection component is disposed in the semiconductor substrate, wherein the protection component is electrically coupled to the deep n-well.

Abstract: A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a semiconductor substrate, at least one deep n-well in the semiconductor substrate, at least one p-channel metal-oxide-semiconductor transistor in the deep n-well, at least one n-channel metal-oxide-semiconductor transistor outside of the deep n-well, an first interconnect structure, and a protection component. Both of the p-channel metal-oxide-semiconductor transistor and the n-channel metal-oxide-semiconductor transistor are disposed in the semiconductor substrate, and are electrically coupled by the first interconnect structure. The protection component is disposed in the semiconductor substrate, wherein the protection component is electrically coupled to the deep n-well.

Abstract: A novel semiconductor device structure includes a first-conductivity-type semiconductor substrate, an isolated region, a first-conductivity-type MOS region, and a second-conductivity-type MOS region. A first-conductivity-type MOS transistor locates in the first-conductivity-type MOS region with a second-conductivity-type well surrounding, and a first-conductivity-type deep well surrounding the second-conductivity-type well with a second-conductivity-type deep well surrounding. In the second-conductivity-type MOS region, a second-conductivity-type MOS transistor is formed with a first-conductivity-type well surrounding. The first-conductivity-type deep well and the second-conductivity-type deep well are sufficiently reducing the noise and current leakage from other devices or from the semiconductor substrate.

Abstract: A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.

Abstract: A method comprising providing at least one dielectric layer above a semiconductor substrate, the at least one dielectric layer having a top surface and a bottom surface; forming a photoresist layer on the top surface of the at least one dielectric layer; providing a single photomask having at least one first pattern corresponding to a conductive via and at least one second pattern corresponding to a conductive trace; patterning the photoresist layer using the single photomask, for forming a trench in the photoresist corresponding to the conductive trace and an opening in a bottom surface of the trench corresponding to the via with a single photo exposure step; and etching the dielectric through the photoresist layer to form the trench and via therein. This application also relates to photomasks for use in the methods of this application.

Abstract: A microelectronic device including a substrate having a top metal layer, a first passivation layer overlying the substrate and wherein the passivation layer includes a via defined at least in part by a side wall of the passivation layer, and wherein the via overlies the top metal layer, a dielectric spacer positioned the via and the spacer having and inner wall with arcuate shape, an the electrically conductive redistribution layer having a portion positioned overlying the inner wall of the spacer and wherein the redistribution layer includes a portion in electrical contact with the top metal layer.

Abstract: Form a butted contact in an SRAM memory device by exposing a contact region on the surface of a doped semiconductor substrate and a conductor stack above a field oxide region on the surface of the substrate. Form an interpolysilicon silicon oxide dielectric layer over the device with an opening framing the contact region and the butt end of the conductor stack near the contact region. Form an undoped upper polysilicon layer on the surface of the SRAM device covering the dielectric layer, the contact region, and the butt end of the conductor stack and then patterned into interconnect and load resistance parts. Form a Vcc mask on the surface of the undoped upper polysilicon layer with a window framing the dielectric layer, the contact region, and the butt end of the conductor stack, leaving an exposed region of the undoped upper polysilicon layer.

Abstract: Form a butted contact in an SRAM memory device by exposing a contact region on the surface of a doped semiconductor substrate and a conductor stack above a field oxide region on the surface of the substrate. Form an interpolysilicon silicon oxide dielectric layer over the device with an opening framing the contact region and the butt end of the conductor stack near the contact region. Form an undoped upper polysilicon layer on the surface of the SRAM device covering the dielectric layer, the contact region, and the butt end of the conductor stack and then patterned into interconnect and load resistance parts. Form a Vcc mask on the surface of the undoped upper polysilicon layer with a window framing the dielectric layer, the contact region, and the butt end of the conductor stack, leaving an exposed region of the undoped upper polysilicon layer.

Abstract: The present invention is a method for preventing backside polysilicon peeling in 4T+2R SRAM process. This invention utilizes forming oxide cap layer on the backside of the wafer to protect the backside polysilicon. Thus, the backside polysilicon is free from peeling and damage.

Abstract: A process for fabricating a polycide SAC structure, for a MOSFET device, has been developed. This process features a polycide SAC structure, comprised of tungsten silicide on in situ doped polysilicon, using tungsten hexafluoride and dichlorosilane as reactants for deposition of tungsten silicide. A first thermal anneal treatment is performed prior to polycide patterning, supplying protection to exposed tungsten silicide sides, during the patterning procedure. A second thermal anneal treatment is performed after polycide patterning, and prior to a silicon oxide deposition, offering protection to the exposed top surface of tungsten silicide, during the silicon oxide deposition.