Patents by Inventor Hung Chen
Hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250149851Abstract: A laser module is provided. The laser module includes a substrate, a laser diode and a diffuser. The substrate has a surface and a base plane, wherein the base plane is parallel to the surface. The laser diode is disposed on the surface. The diffuser is disposed above the laser diode, wherein an included angle is formed between the diffuser and the base plane, and the included angle is greater than 5 degrees.Type: ApplicationFiled: November 1, 2024Publication date: May 8, 2025Inventors: Yi-Min CHEN, Kai-Hung CHENG, Ming-Jing LEE, Jung-Tang CHU
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Publication number: 20250151383Abstract: A semiconductor device including fin field-effect transistors, includes a first gate structure extending in a first direction, a second gate structure extending the first direction and aligned with the first gate structure in the first direction, a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction, a fourth gate structure extending the first direction, aligned with the third gate structure and arranged in parallel with the second gate structure, an interlayer dielectric layer disposed between the first to fourth gate electrodes, and a separation wall made of different material than the interlayer dielectric layer and disposed between the first and third gate structures and the second and fourth gate structures.Type: ApplicationFiled: December 26, 2024Publication date: May 8, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chen HO, Hung Chih HU, Hung Cheng YU, Ju Ru HSIEH
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Publication number: 20250149379Abstract: A method includes following steps. A semiconductor fin is formed on a substrate. A shallow trench isolation (STI) region is formed around a lower portion of the semiconductor fin. An STI protection layer is over the STI region. After forming the STI protection layer, source/drain recesses are etched in the semiconductor fin. Source/drain epitaxial regions are formed in the source/drain recesses.Type: ApplicationFiled: November 2, 2023Publication date: May 8, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Hung CHEN, Yen-Chun HUANG, Yu-Wei CHOU, Zhen-Cheng WU
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Publication number: 20250147268Abstract: A driving mechanism for moving an optical element is provided. The driving mechanism includes a fixed part, a movable part, and a driving assembly. The movable part is movably connected to the fixed part for holding the optical element. The driving assembly is configured for moving the movable part relative to the fixed part.Type: ApplicationFiled: November 8, 2023Publication date: May 8, 2025Inventors: De Shiang CHEN, Kun-Shih LIN, Wei-Jhe SHEN, Chen-Hung CHAO, Sin-Jhong SONG
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Publication number: 20250147068Abstract: A low friction horizontal probing fixture includes two rails of a base unit and two slide units respectively disposed on and being slidable along the rails. Each slide unit has a slide seat that is disposed adjacent to a respective one of the rails, rolling members that are connected to the slide seat and that are rollable on the respective rail so that the slide seat is movable along the respective rail, and a lock mechanism that is disposed on the slide seat and that is operable to position the slide seat relative to the respective rail. A guiding member is connected co-movably to the slide units.Type: ApplicationFiled: November 7, 2023Publication date: May 8, 2025Inventors: Kuan-Hung Chen, Li-Cheng Richard Zai
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Publication number: 20250150062Abstract: A latch calibration system includes a latch, a clock circuit and a calibration circuit. Latch latches logic data from a data node in an internal node. Latch includes two transistors respectively coupled between data node and internal node. Clock circuit generates first and second clock control signals. Calibration circuit is coupled to clock circuit and latch, and includes two bootstrap circuits coupled to clock circuit respectively. First bootstrap circuit generates a third clock control signal according to first clock control signal, which is output to a gate of first transistor. a high level of third clock control signal is greater than that of first clock control signal. Second bootstrap circuit generates a fourth clock control signal according to the second clock control signal, which is output to a gate of second transistor. A low level of fourth clock control signal is less than that of second clock control signal.Type: ApplicationFiled: June 18, 2024Publication date: May 8, 2025Inventors: Hung-Lin WU, Chih-Wen YANG, Yu-Chen LO
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Publication number: 20250147349Abstract: A display device includes a display panel and a switch panel. The switch panel includes a first substrate disposed on the display panel, a shielding pattern layer, a light transmitting layer, pixel electrodes disposed on the light transmitting layer, a second substrate disposed on the pixel electrodes, and the liquid crystal layer disposed between the first substrate and the second substrate. The shielding pattern layer is disposed on the first substrate and includes opening parts and light shielding parts arranged alternately with the opening parts. Each of the light shielding parts has a first thickness. The light transmitting layer is disposed on the shielding pattern layer and includes filling parts filling the opening parts and extending parts arranged alternately with the filling parts. Each of the filling parts has a second thickness greater than the first thickness.Type: ApplicationFiled: October 1, 2024Publication date: May 8, 2025Inventors: Yu-Syuan LIN, Chun-Liang LIN, Chun-Ting HSIAO, Peng-Yu CHEN, Chih-Hung TSAI
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Publication number: 20250149513Abstract: A display device includes a first pixel and a second pixel. The first pixel includes first light-emitting diodes. Each first light-emitting diode includes a first bottom semiconductor layer and a first top semiconductor layer stacked along a vertical direction. The second pixel includes second light-emitting diodes. Each second light-emitting diode includes a second bottom semiconductor layer and a second top semiconductor layer stacked along the vertical direction. In one of the first light-emitting diodes of the first pixel, a first mesa region is located in a first direction of a first overlap region, and in another of the first light-emitting diodes of the first pixel, the first mesa region is located in a second direction opposite to the first direction of the first overlap region. In each second light-emitting diode of the second pixel, a second mesa region is located in the second direction of a second overlap region.Type: ApplicationFiled: September 8, 2024Publication date: May 8, 2025Applicant: AUO CorporationInventors: Ming-Lung Chen, Kun-Cheng Tien, Chien-Hung Kuo, June Woo Lee
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Publication number: 20250144150Abstract: The present invention provides a preparation method of pharmaceutical composition for treating chronic stroke, involving injection via brain into the cranium of a patient having chronic stroke for six months or more; the pharmaceutical composition is a suspension at least comprising adipose-derived stem cells treated by cell expansion, an active synergistic component and a growth factor, wherein the expression level of CD34 and CD45 of the adipose-derived stem cells treated by cell expansion is 10% or less, and the expression level of CD90 and CD105 is 90% or more; the active synergistic component is an extracellular vesicle; the growth factor is at least one selected from the group consisting of HGF, G-CSF, Fractalkine, IP-10, EGF, IL-1?, IL-1?, IL-4, IL-5, IL-13, IFN?, TGF? and sCD40L. The present invention overcomes the limitations of previous cell therapy and provides a cell-based preparation that is clinically safe and therapeutically effective for chronic cerebral stroke.Type: ApplicationFiled: January 8, 2025Publication date: May 8, 2025Inventors: Po-Cheng Lin, Pi-Chun Huang, Chia-Hsin Lee, Ming-Hsi Chuang, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang, Yi-Chun Lin, Yu-Chen Tsai, Peggy Leh Jiunn Wong, Ruei-Yue Liang
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Publication number: 20250144474Abstract: Provided is a sensing and adaptation method for exercise. The method is applied to a sensing and adaptation device for exercise and includes the following steps: generating an exercise game and a first resistance setting to an exercise equipment according to a first exercise target data; receiving an exercise interactive data of a user operating the exercise game from the exercise equipment; generating a reaction-time data according to a stage data of the exercise game and the exercise interactive data and generating an operation trajectory data according to the first resistance setting, the stage data and the exercise interactive data; calculating a deviation degree of the operation trajectory data; calculating a second exercise target data according to the deviation degree; generating a second resistance setting and updating the exercise game according to the second exercise target, and transmitting the second resistance setting to the exercise equipment.Type: ApplicationFiled: November 30, 2023Publication date: May 8, 2025Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventors: Zhi-Ying CHEN, Jia-Hao WANG, Yun-Cheng JHONG, Chia-Hung TSENG, Chien-Der LIN
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Publication number: 20250149797Abstract: An antenna module includes a ground radiator, a first antenna, and a second antenna. The first antenna comprises a first radiator, a second radiator, and a third radiator. The first radiator and the second radiator resonate at a low frequency band and a first high frequency band, and a part of the first radiator and the third radiator resonate at a second high frequency band. The second antenna includes a fourth radiator, the second radiator, and a connecting section. The connecting section is connected between the fourth radiator and the second radiator. A part of the fourth radiator, the connecting section, and the second radiator resonate at the low frequency band and the second high frequency band, and the fourth radiator, the connecting section, and a part of the second radiator resonate at the first high frequency band.Type: ApplicationFiled: July 11, 2024Publication date: May 8, 2025Applicant: PEGATRON CORPORATIONInventors: Chao-Hsu Wu, Chien-Yi Wu, Hao-Hsiang Yang, Tse-Hsuan Wang, Chih-Wei Liao, Hau Yuen Tan, Shih-Keng Huang, Chia-Hung Chen
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Publication number: 20250147245Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a photonic integrated circuit component, an electric integrated circuit component, a lens and an optical signal port. The photonic integrated circuit component comprises an optical input/output portion configured to transmit and receive optical signal. The electric integrated circuit component is electrically connected to the photonic integrated circuit component. The lens is disposed on a sidewall of the photonic integrated circuit component. The optical signal port is optically coupled to the optical input/output portion.Type: ApplicationFiled: November 7, 2023Publication date: May 8, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chih Lin, Hsuan-Ting Kuo, Cheng-Yu Kuo, Yen-Hung Chen, Chia-Shen Cheng, Chao-Wei Li, Ching-Hua Hsieh, Wen-Chih Chiou
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Patent number: 12292585Abstract: The present application provides an aperture assembly. The aperture assembly is used in an optical lens system. The aperture assembly includes a plate including a hollow portion and a non-hollow portion. The hollow portion is configured to define an aperture of the optical lens system, wherein the contour of the hollow portion has a non-circular shape. The aperture assembly can prevent the size of the aperture from being reduced as the size of the plate is reduced in a case that a circular aperture is applied to the plate. The present application also realizes an aperture adjustment for a non-circular aperture.Type: GrantFiled: October 24, 2021Date of Patent: May 6, 2025Assignees: SINTAI OPTICAL (SHENZHEN) CO., LTD., ASIA OPTICAL CO., INC.Inventors: Chun-Hung Huang, Tsung-tse Chen
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Patent number: 12290917Abstract: An object pose estimation system, an execution method thereof and a graphic user interface are provided. The execution method of the object pose estimation system includes the following steps. A feature extraction strategy of a pose estimation unit is determined by a feature extraction strategy neural network model according to a scene point cloud. According to the feature extraction strategy, a model feature is extracted from a 3D model of an object and a scene feature is extracted from the scene point cloud by the pose estimation unit. The model feature is compared with the scene feature by the pose estimation unit to obtain an estimated pose of the object.Type: GrantFiled: October 19, 2021Date of Patent: May 6, 2025Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Dong-Chen Tsai, Ping-Chang Shih, Yu-Ru Huang, Hung-Chun Chou
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Patent number: 12293917Abstract: A chemical mechanical planarization system includes a chemical mechanical planarization pad that rotates during a chemical mechanical planarization process. A chemical mechanical planarization head places a semiconductor wafer in contact with the chemical mechanical planarization pad during the process. A slurry supply system supplies a slurry onto the pad during the process. A pad conditioner conditions the pad during the process. An impurity removal system removes debris and impurities from the slurry.Type: GrantFiled: June 23, 2021Date of Patent: May 6, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Te-Chien Hou, Po-Chin Nien, Chih Hung Chen, Ying-Tsung Chen, Kei-Wei Chen
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Patent number: 12294543Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a base station, an indication that a plurality of physical downlink shared channel (PDSCH) communications are associated for purposes of demodulation reference signal bundling. The UE may determine whether a phase continuity is to be maintained for the plurality of PDSCH communications based at least in part on respective quasi-co-location assumptions for the plurality of PDSCH communications. The UE may process the plurality of PDSCH communications based at least in part on whether the phase continuity is to be maintained Numerous other aspects are provided.Type: GrantFiled: July 28, 2020Date of Patent: May 6, 2025Assignee: Qualcomm IncorporatedInventors: Huilin Xu, Wanshi Chen, Krishna Kiran Mukkavilli, Jing Lei, Yuchul Kim, Hung Dinh Ly, Hwan Joon Kwon, Peter Gaal, Gokul Sridharan, Chao Wei
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Patent number: 12294361Abstract: An output stage of an Ethernet transmitter is provided. The output stage is coupled to a resistor and includes a first output terminal, a second output terminal, a first transistor, and a first transistor group. The resistor is coupled between the first output terminal and the second output terminal. The first transistor has a first source, a first drain, and a first gate, the first source being coupled to a first reference voltage and the first drain being coupled to the second output terminal. The first transistor group is coupled to the first reference voltage and the first output terminal. The first transistor group includes multiple transistors which are connected in parallel, and the magnitude of the current flowing to the first output terminal is related to the number of transistors that are turned on.Type: GrantFiled: December 5, 2022Date of Patent: May 6, 2025Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chien-Hui Tsai, Hung-Chen Chu, Yung-Tai Chen
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Patent number: 12294460Abstract: A user equipment (UE) and a method for transmitting hybrid automatic repeat request (HARQ) feedback are provided. The method includes: receiving a physical uplink control channel (PUCCH) configuration that indicates a specific PUCCH format of a PUCCH and whether a sidelink (SL) HARQ feedback is allowed to be transmitted on the PUCCH; generating a first HARQ feedback in response to first data received via a physical downlink shared channel (PDSCH); generating a second HARQ feedback in response to second data received via a physical sidelink shared channel (PSSCH); and transmitting uplink control information (UCI) including at least a portion of the first HARQ feedback and at least a portion of the second HARQ feedback via the PUCCH in a case that the PUCCH configuration indicates that the SL HARQ feedback is allowed to be transmitted on the PUCCH and the first HARQ feedback overlaps the second HARQ feedback in a time domain.Type: GrantFiled: August 14, 2020Date of Patent: May 6, 2025Assignee: SHARP KABUSHIKI KAISHAInventors: Yu-Hsin Cheng, Yung-Lan Tseng, Mei-Ju Shih, Hung-Chen Chen
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Patent number: 12295191Abstract: A light emitting-diode (LED) display device is provided. The display device comprises plural pixels arranged in array and each pixel includes at least one LED chip. The LED chip is disposed at a cavity of a black matrix (BM) layer and electrical connected to a transistor of a circuit substrate, wherein the transistor is below the BM layer.Type: GrantFiled: September 16, 2021Date of Patent: May 6, 2025Assignee: VISIONLABS CORPORATIONInventors: Hung-Cheng Lin, Hung-Kuang Hsu, Hua-Chen Hsu
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Publication number: 20250134892Abstract: The present disclosure relates to the technical field of medicaments. Particularly, the present disclosure provides a pharmaceutical combination/composition comprising a phosphodiesterase type 5 (PDE5) inhibitor, arginine, and N-acetylcysteine and its applications in treating cardiovascular diseases and erectile dysfunction.Type: ApplicationFiled: February 9, 2023Publication date: May 1, 2025Inventors: Ming Wei CHAO, Chin Hung LIN, Po Tung CHEN