Patents by Inventor Hung Chen

Hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155810
    Abstract: An evaporating concave-convex platform structure of a vapor chamber and a manufacturing method thereof, the structure include a lower plate and an upper plate. The lower plate includes a main plate member and a concave-convex member. The main plate member has a chamber portion dented from one surface thereof and a frame edge surrounding a periphery of the chamber portion. The upper plate is stacked on the lower plate facing a dented surface of the chamber portion. The concave-convex member has a concave-convex surface disposed protrusively from the chamber portion of the lower plate or disposed concavely toward the chamber portion. A connecting portion is disposed to surrounds a periphery of the concave-convex surface. The connecting portion is stacked on the main plate member through the concave-convex surface. The connecting portion is welded to the main plate member.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Inventors: Pang-Hung LIAO, Chih-Wei CHEN
  • Publication number: 20240153920
    Abstract: An electronic device is disclosed. The electronic device includes a first conductive plate and a first electronic component. The first conductive plate includes a first connecting portion. The first electronic component supports the first conductive plate through the first connecting portion. The first connecting portion is electrically connected to the first electronic component and configured to buffer stress from the first conductive plate to the first electronic component.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Applicants: Advanced Semiconductor Engineering, Inc., UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD.
    Inventors: Yi-Hung HOU, Yung-Fa CHEN, Sheng-Chia CHEN
  • Publication number: 20240154008
    Abstract: Provided is a semiconductor device including a substrate, a channel layer, a gate structure, a first doped region, a second doped region, a third doped region and a channel cap layer. The channel layer is located on the substrate. The channel layer has a trench. The gate structure is disposed in the trench. The first doped region and the second doped region are located in the channel layer on two sides of the gate structure. The third doped region is located in the substrate below the channel layer. The channel cap layer is located between the gate structure and the first doped region, between the gate structure and the second doped region, and between the gate structure and the channel layer. An energy band gap of the channel cap layer is larger than an energy band gap of the channel layer.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 9, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Hung Yen, Yu-Ting Chen, Hua-Mao Chen
  • Publication number: 20240153958
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.
    Type: Application
    Filed: January 7, 2024
    Publication date: May 9, 2024
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240153953
    Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung CHEN, Chih-Hung HSIEH, Jhon Jhy LIAW
  • Publication number: 20240153552
    Abstract: A memory array for computing-in-memory (CIM) is disclosed. The memory array for CIM includes a bit cell array, at least one word line and at least one bit line. The bit cell array has a plurality of bit cells, wherein each bit cell is operated at an operating voltage. The at least one word line is electrically connected to the bit cell array, wherein the at least one word line is associated with a first parameter. The at least one bit line is electrically connected to the bit cell array, wherein the bit cells extend along a specific direction, each the at least one bit line has an electrical parameter associated therewith, each the bit cell is associated with a second parameter, a first quantity of the plurality of bit cells of the bit cell array extends along the specific direction, and the memory array determines how an expansion associated with at least one of the first parameter and the second parameter is according to the specific direction.
    Type: Application
    Filed: February 28, 2023
    Publication date: May 9, 2024
    Applicant: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Tian-Sheuan Chang, Wei-Zen Chen, Shyh-Jye Jou, Shu-Hung Kuo, Shih-Hang Kao, Li-Kai Chen
  • Publication number: 20240149388
    Abstract: A method includes polishing a wafer on a polishing pad, performing conditioning on the polishing pad using a disk of a pad conditioner, and conducting a heat-exchange media into the disk. The heat-exchange media conducted into the disk has a temperature different from a temperature of the polishing pad.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 9, 2024
    Inventors: Kei-Wei Chen, Chih Hung Chen
  • Publication number: 20240152187
    Abstract: A foldable electronic device including a first body, a second body, a hinge module, and a cover is provided. The hinge module is connected to the first body and the second body, such that the first body and the second body are rotated relatively to be folded or unfolded via the hinge module. The hinge module has a protruding rod eccentric to a rotation center of the hinge module. The cover is pivoted to the second body and located on a moving path of the protruding rod. The hinge module drives the cover to be rotated relative to the second body via the protruding rod.
    Type: Application
    Filed: October 24, 2023
    Publication date: May 9, 2024
    Applicant: Acer Incorporated
    Inventors: Chun-Hung Wen, Chun-Hsien Chen, Hui-Ping Sun, Wen-Neng Liao, Yu-Ming Lin, Kuan-Lin Chen
  • Publication number: 20240151333
    Abstract: A connecting structure includes a vapor chamber, a heat pipe and a working fluid. The vapor chamber includes a half shell seat, a half shell cover and a first wick structure. The half shell cover is sealed with the half shell seat and a chamber is defined therebetween. The half shell cover has a through hole and an annular wall. The first wick structure is laid on an inner surface of the half shell cover and extended into the annular wall. The heat pipe includes a tube body and a second wick structure. The tube body has an opening and a flange. The heat pipe is upright connected to an outer periphery of the annular wall by the opening. The flange is closely attached to an outer surface of the half shell cover. The second wick structure contacts the first wick structure. The working fluid is disposed in the chamber.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Inventors: Pang-Hung LIAO, Chih-Wei CHEN
  • Publication number: 20240152193
    Abstract: The invention provides a power supply including at least one power output port, at least one status alert component, and at least one output port status monitoring module. The status alert component generates at least one visual prompt based on an alert signal. The output port status monitoring module includes at least one temperature sensor adjacent to the power output port, a microcontroller connected to the temperature sensor and sensing an output current from the power output port, and a reset signal generator connected to the microcontroller. The microcontroller comprises at least one port status alert condition that takes a temperature and the output current of the power output port as decision factors. The microcontroller outputs the alert signal to the status alert component when the port status alert condition is met and maintains the status until a reset signal provided by the reset signal generator is received.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Inventors: Wei-Chen WU, Wen-Hau HU, Hung-Wei YANG, Cheng-Yung LO, Yu-Hao SU, Jian-Zhi HUANG
  • Patent number: 11978740
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
  • Patent number: 11976990
    Abstract: A force sensing method, applied to a force sensing system comprising a plurality of force sensors and a touch sensing surface, comprising: (a) determining a first location of a first object on the touch sensing surface; (b) defining a first force sensing region according to the first location; and (c) computing a first system sensing force which the first object causes to the touch sensing surface according to the first location, and according to at least one sensor sensing force of a first part of the force sensors corresponding to the first force sensing region. The present invention also discloses a force sensing system which uses the above-mentioned force sensing method, and an efficient force sensor calibration method. Noises can be reduced and power consumption can be decreased, since only sensor sensing forces of force sensors near the object are used for computing the system sensing force.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: May 7, 2024
    Assignee: PixArt Imaging Inc.
    Inventors: Ming-Hung Tsai, Chun-Yang Chen, Yen-Po Chen
  • Patent number: 11979130
    Abstract: A transmitter circuit is provided. The transmitter circuit has a first transmission node and a second transmission node and includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a driving circuit. The driving circuit includes a first transistor group, a second transistor group, a third transistor group, and a fourth transistor group. The first resistor is coupled between a first output terminal and the first transmission node. The second resistor is coupled between a second output terminal and the second transmission node. The third resistor is coupled between a third output terminal and the first transmission node. The fourth resistor is coupled between a fourth output terminal and the second transmission node. The first, second, third, and fourth transistor groups are coupled to a first and a second reference voltages and electrically connected to the first, second, third, and fourth output terminals, respectively.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: May 7, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hung-Chen Chu, Chien-Hui Tsai, Yung-Tai Chen
  • Patent number: 11979780
    Abstract: A method for requesting a target system information block (SIB) associated with a target service is provided. The method initiates a dedicated SIB request procedure to send, to a serving cell, a request for the target SIB. The method initiates the dedicated SIB request procedure while the UE has stored at least one SIB segment of a plurality of SIB segments associated with the target SIB, and before the target SIB is successfully assembled based on the plurality of SIB segments. The method transmits, to the serving cell, the request for the target SIB to the serving cell and upon the transmission of the request starts a timer, where a second dedicated SIB request procedure is not allowed to be initiated while the timer is running.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: May 7, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Yung-Lan Tseng, Hung-Chen Chen, Mei-Ju Shih
  • Patent number: 11979854
    Abstract: A method for monitoring paging is provided. The method is performed by a user equipment (UE) and includes actions of receiving a first Physical Downlink Control Channel (PDCCH) addressed to a first Radio Network Temporary Identifier (RNTI), and stopping monitoring a second PDCCH addressed to a second RNTI if the first PDCCH includes a paging stop indicator, where the second RNTI is the same as the first RNTI.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: May 7, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Mei-Ju Shih, Hung-Chen Chen, Yung-Lan Tseng, Chie-Ming Chou
  • Publication number: 20240143038
    Abstract: A portable electronic device including a casing, a heat source, a fan, a heat dissipation fin, a heat pipe and a dust collecting member is provided. The heat source, the fan, the heat dissipation fin, and the heat pipe are located inside the casing, and the heat pipe is thermally coupled between the heat source and the heat dissipation fin. The dust collecting member is detachably assembled to the casing and is inserted into the casing. The heat dissipation fin is disposed as corresponding to the fan, and the dust collecting member is located between the fan and the heat dissipation fin.
    Type: Application
    Filed: October 24, 2023
    Publication date: May 2, 2024
    Applicant: Acer Incorporated
    Inventors: Chun-Hung Wen, Chun-Hsien Chen
  • Publication number: 20240143791
    Abstract: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a search circuitry and a substitution check circuitry. The key generation circuitry is arranged operably to convert a first value of one byte corresponding to a plaintext, an intermediate encryption result, or a round key into a second value of a K-bit according to an 8-to-K lookup table, where K is an integer ranging from 10 to 15 and the second value comprises (K minus 8) bits of a Hamming parity. The substitution check circuitry is arranged operably to employ check formulae corresponding to the 8-to-K lookup table to determine whether an error is occurred during a conversion of the first value of the one byte into the second value of the K-bit, and output an error signal when finding the error, where a total amount of the formulae is K minus 8.
    Type: Application
    Filed: May 30, 2023
    Publication date: May 2, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Wun-Jhe WU, Po-Hung CHEN, Chiao-Wen CHENG, Jiun-Hung YU, Chih-Wei LIU
  • Publication number: 20240147639
    Abstract: An electronic device includes a substrate, a side wiring, a protective film, and a first filler. The substrate has a first surface, a second surface, and a side surface connected between the first surface and the second surface. The side wiring is disposed on the substrate and extends from the first surface to the second surface through the side surface. The protective film is disposed on the side wiring. The side wiring is sandwiched between the substrate and the protective film. An edge of the protective film extends beyond a side wall of the side wiring, and the protective film, the side wall of the side wiring, and the substrate define a gap. The first filler is disposed on the protective film and in the gap, wherein the first filler includes a first material and a plurality of particles mixed within the first material.
    Type: Application
    Filed: October 4, 2023
    Publication date: May 2, 2024
    Applicant: AUO Corporation
    Inventors: Chih-Wen Lu, Fan-Yu Chen, Chun-Yueh Hou, Hsi-Hung Chen
  • Publication number: 20240145482
    Abstract: A thin film transistor includes a bottom gate, a semiconductor layer, a top gate, a first auxiliary conductive pattern, a source, and a drain. The semiconductor layer includes a first semiconductor region, a second semiconductor region, a first heavily doped region, a second heavily doped region, a third heavily doped region, a first lightly doped region, a second lightly doped region, and a third lightly doped region. The first heavily doped region and the second heavily doped region are respectively located on two sides of the first semiconductor region. Two ends of the second semiconductor region are directly connected to the third heavily doped region and the third lightly doped region, respectively. The top gate is electrically connected to the bottom gate. The source and the drain are respectively electrically connected to the third heavily doped region and the second heavily doped region of the semiconductor layer.
    Type: Application
    Filed: December 19, 2022
    Publication date: May 2, 2024
    Applicant: AUO Corporation
    Inventors: Ssu-Hui Lu, Chang-Hung Li, Kuo-Yu Huang, Maw-Song Chen
  • Publication number: 20240142270
    Abstract: A dynamic calibration method for heterogeneous sensors includes: sensing dynamic objects by a first sensor to generate first sensing data; sensing the dynamic objects by a second sensor to generate second sensing data; performing feature matching between the first sensing data and the second sensing data to determine first valid data and second valid data, and identifying a tracked object from the dynamic objects based on the first valid data and the second valid data; performing feature comparison between the first valid data and the second valid data corresponding to the tracked object to calculate data errors between the first sensor and the second sensor; and calculating a calibration parameter based on the first valid data and the second valid data when the number of the data errors exceeds an error threshold, and adjusting the first sensing data and the second sensing data based on the calibration parameter.
    Type: Application
    Filed: January 12, 2023
    Publication date: May 2, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Po-Wei Chen, Chi-Hung Wang, Che-Jui Chang