Abstract: A new method to form a split gate for a flash device in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A film is deposited overlying the substrate. The film comprises a second dielectric layer overlying a first dielectric layer with an electronic-trapping layer therebetween. A masking layer is deposited overlying the film. The masking layer and the film are patterned to expose a part of the substrate and to form a floating gate electrode comprising the electronic-trapping layer. An oxide layer is grown overlying the exposed part of the substrate. The masking layer is removed. A conductive layer is deposited overlying the oxide layer and the second dielectric layer. The conductive layer and the oxide layer are patterned to complete a control gate electrode comprising the conductive layer. The control gate electrode has a first part overlying the floating gate electrode and a second part not overlying the floating gate electrode.

Abstract: A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a semiconductor substrate, a floating gate over the semiconductor substrate, a first, a second, and a third capacitor each having a first plate and sharing a common floating gate as a second plate. The non-volatile memory cell further includes a transistor connected in series with the first capacitor. The gate electrode of the transistor is connected to a wordline of a memory array, and a source/drain region is connected to a bitline.

Abstract: A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.

Abstract: A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.

Abstract: A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.

Abstract: A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a semiconductor substrate, a floating gate over the semiconductor substrate, a first, a second, and a third capacitor each having a first plate and sharing a common floating gate as a second plate. The non-volatile memory cell further includes a transistor connected in series with the first capacitor. The gate electrode of the transistor is connected to a wordline of a memory array, and a source/drain region is connected to a bitline.

Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

Abstract: A programmable non-volatile memory (PNVM) device and method of forming the same compatible with CMOS logic device processes to improve a process flow, the PNVM device including a semiconductor substrate active area; a gate dielectric on the active area; a floating gate electrode on the gate dielectric; an inter-gate dielectric disposed over the floating gate electrode; and, a control gate damascene electrode extending through a dielectric insulating layer in electrical communication with the inter-gate dielectric, the control gate damascene electrode disposed over an upper portion of the floating gate electrode.

Abstract: A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is formed over a first junction for charging the floating gate by electron injection from the source to the floating gate and at least a first dielectric is layered on top of the floating gate to form a second junction. At least a first polycrystalline silicon is layered on top of the first dielectric, the first polycrystalline silicon electrically connected to the source. Electron tunneling provided through the second junction to the floating gate charges the floating gate, thereby increasing the source-coupling ratio of the floating gate and increasing the efficiency of storing electrical charge.

Abstract: Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.

Abstract: Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.

Abstract: A method of fabricating an embedded flash memory device. A substrate having a memory area is provided. A device is formed on the substrate in the memory area. A conductive layer is formed over the substrate to cover the device in the memory area. A conformal insulating layer is formed on the conductive layer and the substrate. The insulating layer is removed at an edge of the memory area. By anisotropic etching, the insulating layer and part of the conductive layer is removed to form a control gate on the sidewall of the device. Thus, polysilicon residue caused by the conventional control gate process does not occur.

Abstract: A method of forming a semiconductor device comprises forming a gate dielectric layer and a gate electrode over the gate dielectric layer on a semiconductor substrate, partially removing the gate dielectric layer to form two recesses separated by the gate dielectric layer and disposed substantially under the gate electrode, and substantially filling the two recesses with an oxide layer and a material layer to form two separated regions operable to each hold an electrical charge.

Abstract: A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased.

Abstract: A new method to form a split gate for a flash device in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A film is deposited overlying the substrate. The film comprises a second dielectric layer overlying a first dielectric layer with an electronic-trapping layer therebetween. A masking layer is deposited overlying the film. The masking layer and the film are patterned to expose a part of the substrate and to form a floating gate electrode comprising the electronic-trapping layer. An oxide layer is grown overlying the exposed part of the substrate. The masking layer is removed. A conductive layer is deposited overlying the oxide layer and the second dielectric layer. The conductive layer and the oxide layer are patterned to complete a control gate electrode comprising the conductive layer. The control gate electrode has a first part overlying the floating gate electrode and a second part not overlying the floating gate electrode.

Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

Abstract: A non-volatile memory device and a method for fabricating the non-volatile memory device employ at least one charge storage dot formed upon a substrate. At least one of an oxidation inhibiting layer and a charge storage enhancing layer is formed upon the charge storage dot. A silicon nitride material layer may simultaneously provide oxidation inhibiting properties and charge storage enhancing properties. The non-volatile memory device is formed with enhanced performance.

Abstract: A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.

Abstract: A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased.