Abstract: A glowing golf ball is provided. A mounting hole is mounted in a light permeable ball and a light emitting member is mounted in the mounting hole. The light emitting member consists of a tube, a light emitting cap, a miniature battery, and a tube base. The tube is provided with a mounting room for mounting the light emitting cap. A light source is disposed on the light emitting cap and the miniature battery is fixed on the tube base. When the tube base and the tube are covered and fixed by each other, the miniature battery and the light source of the light emitting cap are electrically connected. Thus the light source emits light for allowing golf players to see flight paths and final landing positions of the golf ball in a more eye-catching way under poor light condition.

Abstract: A glowing golf ball is provided. A mounting hole is mounted in a light permeable ball and a light emitting member is mounted in the mounting hole. The light emitting member consists of a tube, a light emitting cap, a miniature battery, and a tube base. The tube is provided with a mounting room for mounting the light emitting cap. A light source is disposed on the light emitting cap and the miniature battery is fixed on the tube base. When the tube base and the tube are covered and fixed by each other, the miniature battery and the light source of the light emitting cap are electrically connected. Thus the light source emits light for allowing golf players to see flight paths and final landing positions of the golf ball in a more eye-catching way under poor light condition.

Abstract: The present disclosure provides a socket structure including a casing, a main body, a frame and a cover. The casing includes plural lateral walls, a bottom, an opening and an accommodation space. The opening is defined by the lateral walls. The accommodation space is defined by the lateral walls and the bottom and is in communication with the opening. The main body is disposed in the accommodation space and includes a circuit board and a connection port disposed on the circuit board. The frame includes at least one plate and a first extending portion. The plate surrounds the periphery of the opening. The first extending portion is extended from the plate and is connected to one of the lateral walls. The cover covers the opening and includes a through hole. The through hole is configured to allow a plug to pass through and connect to the connection port.

Abstract: The present disclosure provides a socket structure including a casing, a main body, a frame and a cover. The casing includes plural lateral walls, a bottom, an opening and an accommodation space. The opening is defined by the lateral walls. The accommodation space is defined by the lateral walls and the bottom and is in communication with the opening. The main body is disposed in the accommodation space and includes a circuit board and a connection port disposed on the circuit board. The frame includes at least one plate and a first extending portion. The plate surrounds the periphery of the opening. The first extending portion is extended from the plate and is connected to one of the lateral walls. The cover covers the opening and includes a through hole. The through hole is configured to allow a plug to pass through and connect to the connection port.

Abstract: A baseband system includes: an estimation and compensation circuit estimating frequency-independent non-ideal effects based on an original IQ signal pair, and compensating the original IQ signal pair based on a result of the estimation to obtain a compensated IQ signal pair; a channel estimation and equalization circuit performing channel estimation and equalization based on the compensated IQ signal pair to obtain an equalized IQ signal pair; and a tracking and compensation circuit obtaining a result of tracking of residual quantities of the aforesaid non-ideal effects based on the equalized IQ signal pair, and compensating the equalized IQ signal pair based on the result of the tracking to obtain an output IQ signal pair.

Abstract: A communication system includes a baseband circuit, a transmitting end circuit, and a receiving end circuit is disclosed. The transmitting end circuit includes a digital analog conversion circuit and a transmitting end filtering circuit. The receiving end circuit includes a receiving end amplifying circuit, a receiving end filtering circuit, and an analog digital conversion circuit. A first data signal is transmitted to the analog digital conversion circuit through the digital analog conversion circuit and the transmitting end filtering circuit, so that the baseband circuit obtains a first compensation parameter. A second data signal is transmitted to the receiving end filtering circuit, the receiving end amplifying circuit and the analog digital conversion circuit through the digital analog conversion circuit and the transmitting end filtering circuit, so that the baseband circuit obtains a second compensation parameter.

Abstract: A communication system includes a baseband circuit, a transmitting end circuit, and a receiving end circuit is disclosed. The transmitting end circuit includes a digital analog conversion circuit and a transmitting end filtering circuit. The receiving end circuit includes a receiving end amplifying circuit, a receiving end filtering circuit, and an analog digital conversion circuit. A first data signal is transmitted to the analog digital conversion circuit through the digital analog conversion circuit and the transmitting end filtering circuit, so that the baseband circuit obtains a first compensation parameter. A second data signal is transmitted to the receiving end filtering circuit, the receiving end amplifying circuit and the analog digital conversion circuit through the digital analog conversion circuit and the transmitting end filtering circuit, so that the baseband circuit obtains a second compensation parameter.

Abstract: A baseband system includes: an estimation and compensation circuit estimating frequency-independent non-ideal effects based on an original IQ signal pair, and compensating the original IQ signal pair based on a result of the estimation to obtain a compensated IQ signal pair; a channel estimation and equalization circuit performing channel estimation and equalization based on the compensated IQ signal pair to obtain an equalized IQ signal pair; and a tracking and compensation circuit obtaining a result of tracking of residual quantities of the aforesaid non-ideal effects based on the equalized IQ signal pair, and compensating the equalized IQ signal pair based on the result of the tracking to obtain an output IQ signal pair.

Abstract: A LED backlight driving circuit includes a plurality of driving integrated circuits coupled to a data transmission line and a plurality of selecting circuits respectively connected to the plurality of driving integrated circuits. In an addressing mode, the plurality of selecting circuits are used to select one driving integrated circuit from the plurality of driving integrated circuits to set an address. The plurality of driving integrated circuits can set addresses via input/output pins connected to LEDs. So a number of pins of the driving integrated circuit can be equal to or less than 4, which will rise a yield of the LED backlight driving circuit setting in a PCB or in a glass board.

Abstract: A computer-implemented method and system launches an application with a preferred user interface (UI) language on a device. The method and system receive a voice command from a user to open an application on a device having a computer. The voice command is compared to a stored command language in an audio file device. The system and method initiates opening the application, in response to determining that the voice command matches the stored command language. The application is identified based on the voice command. The system and method determines a preferred language for the software application based on a language file stored on the computer readable medium and the language file being associated with the stored audio file. The method and system opens the application in response to the voice command, and sets the preferred language for a user interface (UI) of the device in response to the determined preferred language.

Abstract: A computer-implemented method and system launches an application with a preferred user interface (UI) language on a device. The method and system receive a voice command from a user to open an application on a device having a computer. The voice command is compared to a stored command language in an audio file device. The system and method initiates opening the application, in response to determining that the voice command matches the stored command language. The application is identified based on the voice command. The system and method determines a preferred language for the software application based on a language file stored on the computer readable medium and the language file being associated with the stored audio file. The method and system opens the application in response to the voice command, and sets the preferred language for a user interface (UI) of the device in response to the determined preferred language.

Abstract: A squelch circuit for operating at high speed and at high frequencies includes a squelch input unit, a low swing pre-amplifier and a sampling and decision circuit. The squelch input unit pre-processes the positive and negative signals of an input signal to generate four pre-processed signals that are paired and sent to the low swing pre-amplifier. The outputs of the low-swing pre-amplifier are then over-sampled by the sampling and decision circuit. Multi-phase clocks are used to control the over-sampling in the sampling and decision circuit. A logic circuit then determines if the state of the input signal based on multiple samples.

Abstract: A multiplying digital-to-analog converter (MDAC) stage includes a plurality of second capacitances in parallel selectively connected between an input node and an amplifier input and between a corresponding plurality of digital reference signals, which can include a pseudo-random first calibration signal, and the amplifier input. A pipelined ADC incorporating a series of such MDAC stages includes a multiplier connected to the last MDAC stage of the series, a low-pass filter for filtering output of the multiplier and outputting a DC component, and an encoder for receiving output of the MDAC stages and generating a digital output signal and for compensating the digital output signal with the DC component. Background calibration of the ADC includes applying the first calibration signal to a second capacitance of the MDAC stage during a hold phase, and filtering the first calibration signal from the digital output of the pipelined analog-to-digital converter.

Abstract: A squelch circuit for operating at high speed and at high frequencies includes a squelch input unit, a low swing pre-amplifier and a sampling and decision circuit. The squelch input unit pre-processes the positive and negative signals of an input signal to generate four pre-processed signals that are paired and sent to the low swing pre-amplifier. The outputs of the low-swing pre-amplifier are then over-sampled by the sampling and decision circuit. Multi-phase clocks are used to control the over-sampling in the sampling and decision circuit. A logic circuit then determines if the state of the input signal based on multiple samples.

Abstract: A digital frequency comparator includes two double-edge triggered flip-flops and a combination logic. Each of the double-edge triggered flip-flops includes two D-type flip-flops and two multiplexers. The first D-type flip-flop receives a first reference clock pulse and is triggered by a data signal. The second D-type flip-flop receives the first reference clock pulse and is triggered by the reverse of the data signal. The first multiplexer provides the output of the first D-type flip-flop when the data signal is 1 and the output of the second D-type flip-flop when the data signal is 0. The second multiplexer provides the output of the first D-type flip-flop when the data signal is 0 and the output of the second D-type flip-flop when the data signal is 1. The combination logic enables an UP pulse when the data signal transmission clock is faster in frequency than the first reference clock signal.

Abstract: A current output circuit for use in a digital-to-analog converter is disclosed. The current output circuit includes a current source for providing a driving current, and a first output circuit coupled with the current source. The first output circuit includes a first metal-oxide semiconductor (MOS) transistor device having a source electrode thereof connected to the current source in series, a first voltage amplifier coupled between the source electrode and a gate electrode of the first MOS transistor device for keeping a voltage of the source electrode substantially constant, and a first controlled switch coupled between an operational voltage and the gate electrode of the first MOS transistor device for being switched ON or OFF in response to a first digital control signal, and allowing the driving current to be outputted from a drain electrode of the MOS transistor device when the first controlled switch is switched ON.

Abstract: The present invention discloses a current feedback operational amplifier, whose input ends are connected to a first amplifier which transmits an output to the gate terminals of at least one input pair of current switches, and the source terminal of one transistor of the input pair of current switches is connected to one of the input ends. Therefore, a negative feedback loop will be established by the first amplifier and the input pair of current switches. By means of the negative feedback loop, the input impedance, offset voltage and gain error are all reduced. The input impedance of the present invention is reduced as 1/1+A times as the original one. Therefore, the aspect ratio of the transistors of the input pair of current switches is reduced.

Abstract: A digital frequency comparator for clock-pulse recovery with “non-return-to-zero data transmission” includes a first double-edge triggered D flip-flop, a second double-edge triggered D flip-flop, and a combination logic. Firstly, the first double-edge triggered D flip-flop receives a data signal and a first reference clock signal, then makes use of the positive-and-negative triggering to output a first state signal and a second state signal of the first reference clock signal. Secondly, the second double-edge triggered D flip-flop receives a data signal and a second reference clock signal, then makes use of the positive-and-negative triggering to output a first state signal and a second state signal of the second reference clock signal. The phase angle of the second reference clock signal is 90-degree lagging behind the phase angle of the first reference clock signal.

Abstract: The present invention discloses a DC offset canceling circuit applied in a variable gain amplifier. The DC offset canceling circuit comprises a transconductance amplifier and at least one internal capacitor to function as a filter. The input of the transconductance amplifier is electrically connected to the output of the variable gain amplifier, and the output of the transconductance amplifier and the at least one internal capacitor are electrically connected to the input of the variable gain amplifier to form a feedback loop. To cooperate with the function of the DC offset cancelation, the input stage of the variable gain amplifier comprises an auxiliary differential pair.

Abstract: The present invention discloses a current feedback operational amplifier, whose input ends are connected to a first amplifier which transmits an output to the gate terminals of at least one input pair of current switches, and the source terminal of one transistor of the input pair of current switches is connected to one of the input ends. Therefore, a negative feedback loop will be established by the first amplifier and the input pair of current switches. By means of the negative feedback loop, the input impedance, offset voltage and gain error are all reduced. The input impedance of the present invention is reduced as 1/1+A times as the original one. Therefore, the aspect ratio of the transistors of the input pair of current switches is reduced.