Abstract: A digital frequency comparator for clock-pulse recovery with “non-return-to-zero data transmission” includes a first double-edge triggered D flip-flop, a second double-edge triggered D flip-flop, and a combination logic. Firstly, the first double-edge triggered D flip-flop receives a data signal and a first reference clock signal, then makes use of the positive-and-negative triggering to output a first state signal and a second state signal of the first reference clock signal. Secondly, the second double-edge triggered D flip-flop receives a data signal and a second reference clock signal, then makes use of the positive-and-negative triggering to output a first state signal and a second state signal of the second reference clock signal. The phase angle of the second reference clock signal is 90-degree lagging behind the phase angle of the first reference clock signal.

Abstract: The present invention discloses a DC offset canceling circuit applied in a variable gain amplifier. The DC offset canceling circuit comprises a transconductance amplifier and at least one internal capacitor to function as a filter. The input of the transconductance amplifier is electrically connected to the output of the variable gain amplifier, and the output of the transconductance amplifier and the at least one internal capacitor are electrically connected to the input of the variable gain amplifier to form a feedback loop. To cooperate with the function of the DC offset cancelation, the input stage of the variable gain amplifier comprises an auxiliary differential pair.

Abstract: The present invention discloses a current feedback operational amplifier, whose input ends are connected to a first amplifier which transmits an output to the gate terminals of at least one input pair of current switches, and the source terminal of one transistor of the input pair of current switches is connected to one of the input ends. Therefore, a negative feedback loop will be established by the first amplifier and the input pair of current switches. By means of the negative feedback loop, the input impedance, offset voltage and gain error are all reduced. The input impedance of the present invention is reduced as 1/1+A times as the original one. Therefore, the aspect ratio of the transistors of the input pair of current switches is reduced.

Abstract: The present invention discloses a DC offset canceling circuit applied in a variable gain amplifier. The DC offset canceling circuit comprises a transconductance amplifier and at least one internal capacitor to function as a filter. The input of the transconductance amplifier is electrically connected to the output of the variable gain amplifier, and the output of the transconductance amplifier and the at least one internal capacitor are electrically connected to the input of the variable gain amplifier to form a feedback loop. To cooperate with the function of the DC offset cancelation, the input stage of the variable gain amplifier comprises an auxiliary differential pair.

Abstract: A fully differential double edge triggered flip-flop stores and outputs first and second fully differential input values on leading and trailing edges of a clock. The flip-flop includes a first fully differential master circuit, a second fully differential master circuit and a fully differential slave circuit. The first master circuit stores the first input value during the period from the leading edge to trailing edge of the clock. The second master circuit stores the second input value during the period from the trailing edge to leading edge of the clock. The slave circuit is electrically connected to outputs of the first and second master circuits. The slave circuit includes a second repeater as an output end of the flip-flop, outputs the first input value on the trailing edge of the clock, and outputs the second input value on the leading edge of the clock.

Abstract: The present invention discloses a current-steering digital-to-analog converter and unit cells. The present invention proposes an n-well bias control circuit for generating a bias voltage whose magnitude is less than the power voltage, therefore the body effect of the transistors could be reduced. Relatively, the threshold voltage and VGS would be reduced. Therefore, even in a low-voltage operation, each transistor could be operated normally in the saturation region. Besides, the plurality of pairs of current switches could be implemented in the same n-well region, instead of being implemented in different n-well regions with leaving a space among each other. Finally, the chip area would be reduced.

Abstract: The present invention is to provide a low voltage fully differential analog-to-digital converter. The converter consists of an input stage including a plurality of pre-amplifier differential input cells for producing pre-amplified signals, a successive processing stage for receiving pre-amplified signals from the input stages, and a decoder for output converted signals according to the signals from the successive processing stage. Each differential input cell includes first and second differential pre-amplifiers, a bias impedance, and an averaging impedance branch. The first and second differential pre-amplifiers include two transistors, respectively, and differentially amplify a set of input signals. One terminal of the bias impedance is connected to a high supplied voltage while the other terminal of the bias impedance is connected to the first and second output terminals through respective pieces of load bearing impedance in order to adjust output voltages of first and second output terminals.

Abstract: The present invention is to provide a low voltage fully differential analog-to-digital converter. The converter consists of an input stage including a plurality of pre-amplifier differential input cells for producing pre-amplified signals, a successive processing stage for receiving pre-amplified signals from the input stages, and a decoder for output converted signals according to the signals from the successive processing stage. Each differential input cell includes first and second differential pre-amplifiers, a bias impedance, and an averaging impedance branch. The first and second differential pre-amplifiers include two transistors, respectively, and differentially amplify a set of input signals. One terminal of the bias impedance is connected to a high supplied voltage while the other terminal of the bias impedance is connected to the first and second output terminals through respective pieces of load bearing impedance in order to adjust output voltages of first and second output terminals.

Abstract: The present invention discloses an n-well bias preset circuit and method. The present invention electrically connects an n-well bias point of the n-well region to the power at the power-on moment to avoid latch-up effect in the CMOS circuit. After several cycles, the n-well bias point is separated from the power, and electrically connected to the output of the n-well bias circuit for reducing the body effect of the CMOS circuit.