Patents by Inventor Hung-Der Su
Hung-Der Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11777302Abstract: A leakage current blocking circuit and a leakage current blocking method for a decoupling capacitor are provided. A first end of the decoupling capacitor is coupled to a power voltage. The leakage current blocking circuit is coupled between a second end of the decoupling capacitor and a ground voltage, and the leakage current blocking circuit includes at least one switch. The at least one switch is used to provide a channel for the decoupling capacitor to be coupled to the ground voltage when the decoupling capacitor is not damaged, and when the decoupling capacitor is damaged, the at least one switch is turned off to block a leakage current of the decoupling capacitor.Type: GrantFiled: July 16, 2021Date of Patent: October 3, 2023Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Hung-Der Su
-
Publication number: 20230116315Abstract: A FinFET with discontinuous channel regions includes M gate-end structure(s), N drain-end structure(s), and a conducting structure. Each gate-end structure includes: a first channel structure including a source region and a first channel region; and a gate structure formed on a surface of the first channel region. Each drain-end structure includes: a second channel structure including a second channel region and a drain region, wherein the second channel region and the first channel region are discontinuous; and a reduced-surface-field structure formed on a surface of the second channel region. The conducting structure couples the first channel region of one of the M gate-end structure(s) with the second channel region of one of the N drain-end structure(s). The FinFET is characterized by a high withstand voltage and a low on-state resistance.Type: ApplicationFiled: September 28, 2022Publication date: April 13, 2023Inventor: HUNG-DER SU
-
Publication number: 20220209523Abstract: A leakage current blocking circuit and a leakage current blocking method for a decoupling capacitor are provided. A first end of the decoupling capacitor is coupled to a power voltage. The leakage current blocking circuit is coupled to between a second end of the decoupling capacitor and a ground voltage, and the leakage current blocking circuit includes at least one switch. The at least one switch is used to provide a channel for the decoupling capacitor to be coupled to the ground voltage when the decoupling capacitor is not damaged, and when the decoupling capacitor is damaged, the at least one switch is closed to block a leakage current of the decoupling capacitor.Type: ApplicationFiled: July 16, 2021Publication date: June 30, 2022Inventor: HUNG-DER SU
-
Patent number: 11243181Abstract: The invention provides a bio-detection device, including a carrier, a plurality of spacers, an electronic circuit, and a package layer, wherein an open platform is formed. The carrier includes a test region and a signal transmission wiring, wherein the test region is configured to carry a fluid under test. The spacers are located on the test region and electrically connected to two different voltage levels to form a capacitor for sensing a capacitance of the fluid. The spacers are connected to the signal transmission wiring. The electronic circuit receives and processes a sensing signal corresponding to the capacitance of the fluid. The package layer covers a portion of the carrier but does not cover the test region. The open platform is formed whereby a user can easily put in the fluid. The open platform has a bottom which includes the test region, and an area of the open platform is defined by the spacers and the package layer.Type: GrantFiled: February 4, 2020Date of Patent: February 8, 2022Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Yu-Lin Yang, Chun-Hao Chang, Min-Da Wu, Hung-Der Su, Da-Hong Qian
-
Publication number: 20200173948Abstract: The invention provides a bio-detection device, including a carrier, a plurality of spacers, an electronic circuit, and a package layer, wherein an open platform is formed. The carrier includes a test region and a signal transmission wiring, wherein the test region is configured to carry a fluid under test. The spacers are located on the test region and electrically connected to two different voltage levels to form a capacitor for sensing a capacitance of the fluid. The spacers are connected to the signal transmission wiring. The electronic circuit receives and processes a sensing signal corresponding to the capacitance of the fluid. The package layer covers a portion of the carrier but does not cover the test region. The open platform is formed whereby a user can easily put in the fluid. The open platform has a bottom which includes the test region, and an area of the open platform is defined by the spacers and the package layer.Type: ApplicationFiled: February 4, 2020Publication date: June 4, 2020Inventors: Yu-Lin Yang, Chun-Hao Chang, Min-Da Wu, Hung-Der Su, Da-Hong Qian
-
Patent number: 10591434Abstract: The invention provides a bio-detection device, including a carrier, a plurality of spacers, an electronic circuit, and a package layer, wherein an open platform is formed. The carrier includes a test region and a signal transmission wiring, wherein the test region is configured to carry a fluid under test. The spacers are located on the test region and electrically connected to two different voltage levels to form a capacitor for sensing a capacitance of the fluid. The spacers are connected to the signal transmission wiring. The electronic circuit receives and processes a sensing signal corresponding to the capacitance of the fluid. The package layer covers a portion of the carrier but does not cover the test region. The open platform is formed whereby a user can easily put in the fluid. The open platform has a bottom which includes the test region, and an area of the open platform is defined by the spacers and the package layer.Type: GrantFiled: April 24, 2017Date of Patent: March 17, 2020Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Yu-Lin Yang, Chun-Hao Chang, Min-Da Wu, Hung-Der Su, Da-Hong Qian
-
Publication number: 20190227018Abstract: The invention provides a bio-detection device, including a carrier, a plurality of spacers, an electronic circuit, and a package layer, wherein an open platform is formed. The carrier includes a test region and a signal transmission wiring, wherein the test region is configured to carry a fluid under test. The spacers are located on the test region and electrically connected to two different voltage levels to form a capacitor for sensing a capacitance of the fluid. The spacers are connected to the signal transmission wiring. The electronic circuit receives and processes a sensing signal corresponding to the capacitance of the fluid. The package layer covers a portion of the carrier but does not cover the test region. The open platform is formed whereby a user can easily put in the fluid. The open platform has a bottom which includes the test region, and an area of the open platform is defined by the spacers and the package layer.Type: ApplicationFiled: April 24, 2017Publication date: July 25, 2019Inventors: Yu-Lin Yang, Chun-Hao Chang, Min-Da Wu, Hung-Der Su, Da-Hong Qian
-
Publication number: 20180306742Abstract: The invention provides a bio-detection device, including a carrier, a plurality of spacers, an electronic circuit, and a package layer, wherein an open platform is formed. The carrier includes a test region and a signal transmission wiring, wherein the test region is configured to carry a fluid under test. The spacers are located on the test region and electrically connected to two different voltage levels to form a capacitor for sensing a capacitance of the fluid. The spacers are connected to the signal transmission wiring. The electronic circuit receives and processes a sensing signal corresponding to the capacitance of the fluid. The package layer covers a portion of the carrier but does not cover the test region. The open platform is formed whereby a user can easily put in the fluid. The open platform has a bottom which includes the test region, and an area of the open platform is defined by the spacers and the package layer.Type: ApplicationFiled: April 24, 2017Publication date: October 25, 2018Inventors: Yu-Lin Yang, Chun-Hao Chang, Min-Da Wu, Hung-Der Su, Da-Hong Qian
-
Patent number: 9627524Abstract: The present invention discloses a high voltage metal oxide semiconductor (HVMOS) device and a method for making same. The high voltage metal oxide semiconductor device comprises: a substrate; a gate structure on the substrate; a well in the substrate, the well defining a device region from top view; a first drift region in the well; a source in the well; a drain in the first drift region, the drain being separated from the gate structure by a part of the first drift region; and a P-type dopant region not covering all the device region, wherein the P-type dopant region is formed by implanting a P-type dopant for enhancing the breakdown voltage of the HVMOS device (for N-type HVMOS device) or reducing the ON resistance of the HVMOS device (for P-type HVMOS device).Type: GrantFiled: March 2, 2010Date of Patent: April 18, 2017Assignee: RICHTEK TECHNOLOGY CORPORATION, R.O.C.Inventors: Tsung-Yi Huang, Huan-Ping Chu, Ching-Yao Yang, Hung-Der Su
-
Patent number: 9590049Abstract: The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.Type: GrantFiled: December 11, 2015Date of Patent: March 7, 2017Assignee: Richtek Technology CorporationInventors: Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang
-
Patent number: 9484437Abstract: The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.Type: GrantFiled: February 8, 2016Date of Patent: November 1, 2016Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Tsung-Yi Huang, Ching-Yao Yang, Wen-Yi Liao, Hung-Der Su, Kuo-Cheng Chang
-
Patent number: 9362384Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.Type: GrantFiled: December 3, 2014Date of Patent: June 7, 2016Assignee: Richtek Technology CorporationInventors: Tzu-Cheng Kao, Jian-Hsing Lee, Jin-Lian Su, Huan-Ping Chu, Hung-Der Su
-
Publication number: 20160155820Abstract: The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.Type: ApplicationFiled: February 8, 2016Publication date: June 2, 2016Applicant: RICHTEK TECHNOLOGY CORPORATIONInventors: Tsung-Yi Huang, Ching-Yao Yang, Wen-Yi Liao, Hung-Der Su, Kuo-Cheng Chang
-
Publication number: 20160099320Abstract: The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.Type: ApplicationFiled: December 11, 2015Publication date: April 7, 2016Applicant: Richtek Technology CorporationInventors: Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang
-
Patent number: 9287394Abstract: The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.Type: GrantFiled: October 9, 2014Date of Patent: March 15, 2016Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Tsung-Yi Huang, Ching-Yao Yang, Wen-Yi Liao, Hung-Der Su, Kuo-Cheng Chang
-
Patent number: 9245746Abstract: The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.Type: GrantFiled: October 8, 2013Date of Patent: January 26, 2016Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang
-
Publication number: 20150137232Abstract: The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.Type: ApplicationFiled: October 9, 2014Publication date: May 21, 2015Applicant: RICHTEK TECHNOLOGY CORPORATIONInventors: Tsung-Yi Huang, Ching-Yao Yang, Wen-Yi Liao, Hung-Der Su, Kuo-Cheng Chang
-
Publication number: 20150079755Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.Type: ApplicationFiled: December 3, 2014Publication date: March 19, 2015Applicant: RICHTEK TECHNOLOGY CORPORATION, R.O.CInventors: Tzu-Cheng Kao, Jian-Hsing Lee, Jin-Lian Su, Huan-Ping Chu, Hung-Der Su
-
Patent number: 8981429Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.Type: GrantFiled: May 20, 2013Date of Patent: March 17, 2015Assignee: Richtek Technology Corporation, R.O.C.Inventors: Chih-Fang Huang, Po-Chin Peng, Tsung-Chieh Hsiao, Ya-Hsien Liu, K. C. Chang, Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang, Tsung-Yu Yang, Ting-Fu Chang
-
Patent number: 8928078Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.Type: GrantFiled: December 25, 2012Date of Patent: January 6, 2015Assignee: Richtek Technology Corporation, R.O.C.Inventors: Tzu-Cheng Kao, Jian-Hsing Lee, Jin-Lian Su, Huan-Ping Chu, Hung-Der Su