Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: In a LED driver using a depletion mode transistor to serve as a current source, the depletion mode transistor is self-biased for providing a driving current to drive at least one LED, thereby requesting no additional control circuit to control the depletion mode transistor. The driving current is independent on the supply voltage coupled to the at least one LED, thereby requesting no additional voltage regulator, reducing the circuit size, and lowering the cost.

Abstract: A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

Abstract: An amplifier circuit with internal zeros provides a second pole in addition to a first pole and two zeros such that the second pole can prevent excessive gain at high frequency, so as to have high-frequency noise under control.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A power supply circuit and a control method are provided, in which the original enable pad and output pad, or the enable pad and feedback pad are used to trim the output voltage of the power supply circuit without extra trim pads.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A fully logic process compatible non-volatile memory cell has a well on a substrate, a pair of source and drain outside the well, a channel between the source and drain, a control gate in the well, and a floating gate having a first portion above the channel, and a second portion above the well. The control gate includes two regions having opposite conductivity types and a third region between the two regions and under the second portion of the floating gate, and thus eliminates the parasitic depletion capacitor in the coupling path of the cell, thereby improving the coupling ratio.

Abstract: A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.

Abstract: A two-step spacer etch is used for the formation of a spacer in CMOS fabrication. A dry etch is first applied to remove part of the spacer material on the silicon substrate and leave a thin layer of the spacer material remained on the silicon substrate. Then, a wet etch is applied to completely remove the thin layer of the spacer material on the silicon substrate. The wet etch has good etch selectivity between the spacer material and silicon, and thus will not damage the surface of the silicon substrate when the spacer is formed. Therefore, the BJT on the silicon substrate is prevented from junction leakage.

Abstract: A booster power management integrated circuit chip includes first and second output pads, a transistor switch coupled between the first and second output pads and having a gate, and a trigger circuit coupled between the first and second output pads and further coupled to the gate of the transistor switch. The trigger circuit drives the transistor switch to conduct when an instantaneous voltage larger than a trigger voltage level is present between the first and second output pads so as to enable electric current to flow through the transistor switch.

Abstract: An amplifier circuit with internal zeros provides a second pole in addition to a first pole and two zeros such that the second pole can prevent excessive gain at high frequency, so as to have high-frequency noise under control.

Abstract: According to the present invention, a semiconductor process for butting contact comprises: providing a substrate on which are formed two adjacent transistor gates; implanting a full area between the two adjacent transistor gates by a tilt angle, to form a lightly doped region of a first conductivity type; forming a heavily doped region of the first conductivity type and a heavily doped region of a second conductivity type in the area between the two adjacent transistor gates, in which the heavily doped region of the second conductivity type overrides the lightly doped region of the first conductivity type, and divides the heavily doped region of the first conductivity type into two areas; depositing a dielectric layer; and forming a butting contact in the dielectric layer which concurrently contacts the two divided heavily doped regions of the first conductivity type.

Abstract: The present invention discloses a level shift circuit which comprises: level shift means for receiving an input of a first operational voltage and generating an output of a second operational voltage; and a current path connecting with a source of the second operational voltage and providing current to the output of the level shift means to speed up output level switching. The circuit preferably further comprises a power consumption control circuit for stopping excess power consumption when the output of the level shift means has substantially accomplished level switching.

Abstract: A fully logic process compatible non-volatile memory cell has a well on a substrate, a pair of source and drain outside the well, a channel between the source and drain, a control gate in the well, and a floating gate having a first portion above the channel, and a second portion above the well. The control gate includes two regions having opposite conductivity types and a third region between the two regions and under the second portion of the floating gate, and thus eliminates the parasitic depletion capacitor in the coupling path of the cell, thereby improving the coupling ratio.