Patents by Inventor Hung-En Tai

Hung-En Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7412090
    Abstract: A method of managing wafer defects includes inspecting each chip in a wafer to generate a unit of wafer defect raw data, using a server to integrate the unit of wafer defect raw data to generate a unit of wafer defect distribution data for recording positions, types, and sizes of defects, using the server to generate a corresponding drawing file according to the unit wafer defect distribution data to show all kinds of defect distributions, and transmitting the drawing file to a terminal such that terminal users can view the defect distributions without receiving the unit of wafer defect raw data.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: August 12, 2008
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Hung-En Tai, Chia-Yun Chen, Sheng-Jen Wang
  • Publication number: 20070129833
    Abstract: A dispatch integration method based on semiconductor manufacturing. When multiple tools are idle, idle messages are sent to a real-time dispatch system through a tool control system and a manufacturing execution system. The real-time dispatch system sorts tool parameters relating to tool efficiency based on a currently executed process using a principal component analysis method, defining weights of each tool according to the defined tool parameters and corresponding factor weights using a linear regression weight formula, calculating tool weights of each tool parameter using a linear regression weight formula, and determining a desired tool for dispatch according to the calculated tool weights.
    Type: Application
    Filed: April 12, 2006
    Publication date: June 7, 2007
    Inventors: Yu-Wen Ho, Hung-En Tai, Chien-Chung Chen
  • Patent number: 7218981
    Abstract: A dispatch integration method based on semiconductor manufacturing. When multiple tools are idle, idle messages are sent to a real-time dispatch system through a tool control system and a manufacturing execution system. The real-time dispatch system sorts tool parameters relating to tool efficiency based on a currently executed process using a principal component analysis method, defining weights of each tool according to the defined tool parameters and corresponding factor weights using a linear regression weight formula, calculating tool weights of each tool parameter using a linear regression weight formula, and determining a desired tool for dispatch according to the calculated tool weights.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: May 15, 2007
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Yu-Wen Ho, Hung-En Tai, Chien-Chung Chen
  • Patent number: 7099729
    Abstract: A semiconductor process and yield analysis integrated real-time management method comprises inspecting a plurality of semiconductor products with a plurality of items to generate and record a plurality of inspecting results during semiconductor process, classifying the semiconductor products as a plurality of groups with a default rule to generate and record an initial data in a database, indexing a plurality of semiconductor product groups and the corresponding initial data from the database by a default product rule and parameter to calculate a corresponding analysis result, and displaying the analysis result according to the indexed semiconductor product groups and the initial data.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: August 29, 2006
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Hung-En Tai, Chien-Chung Chen, Sheng-Jen Wang
  • Patent number: 7079677
    Abstract: An automatic intelligent yield improving and process parameter multivariate analysis system and the analysis method thereof. The system is applied to a computer to set up analysis procedures for analyzing process parameters obtained from each measuring machine in semiconductor testing process by utilizing data mining technology. The system includes a plurality of semiconductor processing nodes having different functions. The system links each of the semiconductor processing node to another semiconductor processing node by a logic means so that the computer can process the semiconductor processing nodes sequentially. The system also links the semiconductor processing nodes by a data connection means to allow microprocessors to load necessary parameter data or wafer lot numbers from corresponding semiconductor processing nodes by a data connection means.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: July 18, 2006
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Hung-En Tai, Sheng-Jen Wang
  • Publication number: 20060050950
    Abstract: A method of managing wafer defects includes inspecting each chip in a wafer to generate a unit of wafer defect raw data, using a server to integrate the unit of wafer defect raw data to generate a unit of wafer defect distribution data for recording positions, types, and sizes of defects, using the server to generate a corresponding drawing file according to the unit wafer defect distribution data to show all kinds of defect distributions, and transmitting the drawing file to a terminal such that terminal users can view the defect distributions without receiving the unit of wafer defect raw data.
    Type: Application
    Filed: September 9, 2004
    Publication date: March 9, 2006
    Inventors: Hung-En Tai, Chia-Yun Chen, Sheng-Jen Wang
  • Publication number: 20060048010
    Abstract: A data analyzing method for a fault detection and classification system. The method includes extracting a set of raw data from a fault detection and classification system, separating the raw data for generating another set of classified data via a predetermined filtering condition, and utilizing a predetermined statistical method for analyzing the classified data.
    Type: Application
    Filed: August 30, 2004
    Publication date: March 2, 2006
    Inventors: Hung-En Tai, Haw-Jyue Luo
  • Patent number: 6999897
    Abstract: A method and related system for semiconductor equipment early warning management. The method includes recording process parameters of each piece of equipment, recording equipment parameters when each piece of equipment is processing, evaluating and recording the quality of semiconductor products and corresponding testing parameters, and analyzing a relationship between the corresponding process parameters, the corresponding equipment parameters, and the quality of semiconductor products of each piece of equipment.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: February 14, 2006
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Hung-En Tai, Chien-Chung Chen, Haw-Jyue Luo, Sheng-Jen Wang
  • Patent number: 6968280
    Abstract: A plurality of lots of wafers, each lot of wafers having a lot number and each wafer of each lot having at least one test parameter generated by performing at least one wafer test item stored in a database, are divided into a high yield group and a low yield group. By analyzing the wafer test parameters of the wafers in the high yield group, a first standard value within a first range is obtained. A first comparison step is then performed to compare each wafer test parameter of each lot in the low yield group with the first standard value and delete lot numbers of lots with wafer test parameters within the first range. Finally, a first amount of residual lots in the low yield group is determined. In response to the first amount of residual lots in the low yield group not equaling to zero, a first searching step is performed to which item of sample test items, in-line QC items and process step items is related to the wafer test item of each residual lot in the low yield group in the database.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: November 22, 2005
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Hung-En Tai, Ching-Ly Yueh
  • Patent number: 6959252
    Abstract: A method for analyzing in-line QCtest parameters is used to analyze a plurality of lots of products, each lot of products having a lot number and being formed using a plurality of equipments. At least one wafer of each lot of products is tested by at least one in-line QC test item to generate an in-line QC test parameter. The in-line QC test item, a sample test item and a wafer test item related to the in-line QC test item are stored in a database. The database further stores the in-line QC test parameter and data of a plurality of lots of high-yield product stocks, such as various test items and test parameters.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: October 25, 2005
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Hung-En Tai, Haw-Jyue Luo
  • Patent number: 6950783
    Abstract: A method and related system for semiconductor equipment prevention maintenance management. The method includes recording process parameters of each piece of equipment, recording equipment parameters when each piece of equipment is processing, evaluating and recording time and cost of prevention maintenance after each piece of equipment runs prevention maintenance, evaluating the quality of semiconductor products, and analyzing a relationship between the corresponding process parameter, the corresponding equipment parameters, prevention maintenance cost, and semiconductor products of each piece of equipment.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: September 27, 2005
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Hung-En Tai, Chien-Chung Chen, Sheng-Jen Wang
  • Publication number: 20050203858
    Abstract: A method and related system for semiconductor equipment prevention maintenance management. The method includes recording process parameters of each piece of equipment, recording equipment parameters when each piece of equipment is processing, evaluating and recording time and cost of prevention maintenance after each piece of equipment runs prevention maintenance, evaluating the quality of semiconductor products, and analyzing a relationship between the corresponding process parameter, the corresponding equipment parameters, prevention maintenance cost, and semiconductor products of each piece of equipment.
    Type: Application
    Filed: March 11, 2004
    Publication date: September 15, 2005
    Inventors: Hung-En Tai, Chien-Chung Chen, Sheng-Jen Wang
  • Publication number: 20050203715
    Abstract: A method and related system for semiconductor equipment early warning management. The method includes recording process parameters of each piece of equipment, recording equipment parameters when each piece of equipment is processing, evaluating and recording the quality of semiconductor products and corresponding testing parameters, and analyzing a relationship between the corresponding process parameters, the corresponding equipment parameters, and the quality of semiconductor products of each piece of equipment.
    Type: Application
    Filed: March 11, 2004
    Publication date: September 15, 2005
    Inventors: Hung-En Tai, Chien-Chung Chen, Haw-Jyue Luo, Sheng-Jen Wang
  • Publication number: 20050187648
    Abstract: A semiconductor process and yield analysis integrated real-time management method comprises inspecting a plurality of semiconductor products with a plurality of items to generate and record a plurality of inspecting results during semiconductor process, classifying the semiconductor products as a plurality of groups with a default rule to generate and record an initial data in a database, indexing a plurality of semiconductor product groups and the corresponding initial data from the database by a default product rule and parameter to calculate a corresponding analysis result, and displaying the analysis result according to the indexed semiconductor product groups and the initial data.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 25, 2005
    Inventors: Hung-En Tai, Chien-Chung Chen, Sheng-Jen Wang
  • Patent number: 6904384
    Abstract: A complex multivariate analysis system is provided. The system has a storage module, a selecting module, an analyzing module, a correlation searching module and a reporting module. The storage module includes a first database and a second database. The first database records at least two data sets, each of the data sets including a plurality of items associated with a manufacturing process and data of the items. The second database records correlations of the items between the two data sets. The selecting module selects a first item from a first data set. The analyzing module analyzes the first item selected by the selecting module and determines whether the data of the first item conform to specifications or not. The correlation searching module searches the second database when the analyzing module determines that the data of the first item do not conform to the specifications, and selects a second item correlated to the first item from a second data set.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: June 7, 2005
    Assignee: Powerchip Semiconductor Corp.
    Inventor: Hung-En Tai
  • Patent number: 6898539
    Abstract: A method for analyzing final test parameters includes the following steps: To retrieve the final test parameters of each product lots by searching a database. To compare the final test parameters to select a representative final test parameter and a representative final test item. To determine if the representative final test item is correlated to a packaging process step. To classify the plurality of product lots into at least a first qualified group and a first failed group according to the representative final test item if there is correlation. To search for the equipment through which the first qualified group or the first failed group had passed in the packaging process step. To determine the equipment having a probability of having processed the first failed group being greater than a probability of having processed the first qualified group.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: May 24, 2005
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Hung-En Tai, Chien-Chung Chen
  • Publication number: 20050004773
    Abstract: A method for analyzing in-line QCtest parameters is used to analyze a plurality of lots of products, each lot of products having a lot number and being formed using a plurality of equipments. At least one wafer of each lot of products is tested by at least one in-line QC test item to generate an in-line QC test parameter. The in-line QC test item, a sample test item and a wafer test item related to the in-line QC test item are stored in a database. The database further stores the in-line QC test parameter and data of a plurality of lots of high-yield product stocks, such as various test items and test parameters.
    Type: Application
    Filed: July 3, 2003
    Publication date: January 6, 2005
    Inventors: Hung-En Tai, Haw-Jyue Luo
  • Patent number: 6828776
    Abstract: The claimed invention method is for analyzing defect inspection parameters. The method includes searching for the defect inspection parameters of a plurality of lots of products from a database, classifying the plurality of lots of products into at least a qualified group and a failed group according to the defect inspection parameters, searching for a process step correlated to a defect inspection item from the database, searching for manufacturing equipment through which the qualified group has passed in the process step and the manufacturing equipment through which the failed group has passed in the process step, and determining the manufacturing equipment through which the probability that the failed group having passed which is greater than that of the qualified group.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: December 7, 2004
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Hung-En Tai, Haw-Jyue Luo
  • Publication number: 20040199358
    Abstract: A complex multivariate analysis systemis provided. The system has a storage module, a selecting module, an analyzing module, a correlation searching module and a reporting module. The storage module includes a first database and a second database. The first database records at least two data sets, each of the data sets including a plurality of items associated with a manufacturing process and data of the items. The second database records correlations of the items between the two data sets. The selecting module selects a first item from a first data set. The analyzing module analyzes the first item selected by the selecting module and determines whether the data of the first item conform to specifications or not. The correlation searching module searches the second database when the analyzing module determines that the data of the first item do not conform to the specifications, and selects a second item correlated to the first item from a second data set.
    Type: Application
    Filed: April 3, 2003
    Publication date: October 7, 2004
    Inventor: Hung-En Tai
  • Publication number: 20040193381
    Abstract: A plurality of lots of wafers, each lot of wafers having a lot number and each wafer of each lot having at least one test parameter generated by performing at least one wafer test item stored in a database, are divided into a high yield group and a low yield group. By analyzing the wafer test parameters of the wafers in the high yield group, a first standard value within a first range is obtained. A first comparison step is then performed to compare each wafer test parameter of each lot in the low yield group with the first standard value and delete lot numbers of lots with wafer test parameters within the first range. Finally, a first amount of residual lots in the low yield group is determined. In response to the first amount of residual lots in the low yield group not equaling to zero, a first searching step is performed to which item of sample test items, in-line QC items and process step items is related to the wafer test item of each residual lot in the low yield group in the database.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 30, 2004
    Inventors: Hung-En Tai, Ching-Ly Yueh