Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: A retainer includes an abutting portion, a protrusion integrally extended from a side of the abutting portion and having a through hole for a lift pull cord to be slidably threaded therethrough, and two opposite upper cantilever portions and two opposite lower cantilever portions integrally extended from another side of the abutting portion. A first positioning groove is provided between the upper and lower cantilever portions for a slat to be embedded in the first positioning groove. Second and third positioning grooves perpendicularly communicating with the first positioning groove are provided between the upper cantilever portions and between the lower cantilever portions respectively for a tilt cord to be inserted in the second and third positioning grooves.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: A three-wheeled cord rolling device includes a driving unit having two torsion spring wheels engaged with each other and a torsion spring connecting the torsion spring wheels, and a cord rolling unit having a cord rolling wheel and two lift transmission cords. The cord rolling wheel is engaged with one of the torsion spring wheels, thereby rotatable with them synchronously. The cord rolling wheel has an axle having upper and lower axial portions and a separating portion connecting the upper and lower axial portions. The lift transmission cords are disposed on the upper and lower axial portions of the axle respectively, thereby capable of being rolled up or released from the upper and lower axial portions of the axle by the rotation of the cord rolling wheel.

Abstract: A dual-torsion-spring cord rolling device includes driving and transmission units. The driving unit has first and second torsion spring gears engaged with each other, a first torsion spring connecting the first and second torsion spring gears, a wheel adjacent to the first torsion spring gear, and a second torsion spring connecting the second torsion spring gear and the wheel. The transmission unit has first and second transmission gears rotatable synchronously by the driving of the second torsion spring gear, and two lift transmission cords attached to the first and second transmission gears respectively.

Abstract: A ladder cord fastening seat for a non-pull window blind includes two vertical posts located opposite to each other and an arc bridge. The ladder cord fastening seat is fastened in a top beam through the two vertical posts. Each of the vertical posts has a cord inserting hole for a ladder cord to be inserted therethrough. The arc bridge is used for fastening the ladder cord. The arc bridge connects the two vertical posts in such a way that an accommodation space is defined to accommodate a transmission member located in the top beam.

Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

Abstract: An environment-friendly material includes 50 wt % to 70 wt % of inorganic mineral powder, 20 wt % to 45 wt % of polyolefin, and 5 wt % to 15 wt % of auxiliary agent. The inorganic mineral powder contains calcium carbonate; the polyolefin may be linear low density polyethylene, low density polyethylene, medium density polyethylene, high density polyethylene, or polypropylene; and the auxiliary agent may be polyolefin elastomer, maleic anhydride grafted polyolefin elastomer, or maleic anhydride grafted polyethylene. The disclosure also provides a manufacturing method of window covering slat using the environment-friendly material and a window covering slat manufactured by the method.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: An environment-friendly material includes 50 wt % to 70 wt % of inorganic mineral powder, 20 wt % to 45 wt % of polyolefin, and 5 wt % to 15 wt % of auxiliary agent. The inorganic mineral powder contains calcium carbonate; the polyolefin may be linear low density polyethylene, low density polyethylene, medium density polyethylene, high density polyethylene, or polypropylene; and the auxiliary agent may be polyolefin elastomer, maleic anhydride grafted polyolefin elastomer, or maleic anhydride grafted polyethylene. The disclosure also provides a manufacturing method of window covering slat using the environment-friendly material and a window covering slat manufactured by the method.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.

Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.