Patents by Inventor Hung-Hsiang Cheng

Hung-Hsiang Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11817481
    Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Hsiang Cheng, Samuel C. Pan
  • Patent number: 11670836
    Abstract: A semiconductor device package includes a substrate, an air cavity, a radiator, and a director. The substrate has a top surface. The air cavity is disposed within the substrate. The air cavity has a first sidewall and a second sidewall opposite to the first sidewall. The radiator is disposed adjacent to the first sidewall of the air cavity. The director is disposed adjacent to the second sidewall of the air cavity.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: June 6, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ting Ruei Chen, Hung-Hsiang Cheng, Guo-Cheng Liao, Yun-Hsiang Tien
  • Publication number: 20220384581
    Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Hung-Hsiang CHENG, Samuel C. PAN
  • Patent number: 11502174
    Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Hsiang Cheng, Samuel C. Pan
  • Publication number: 20220140467
    Abstract: A semiconductor device package includes a substrate, an air cavity, a radiator, and a director. The substrate has a top surface. The air cavity is disposed within the substrate. The air cavity has a first sidewall and a second sidewall opposite to the first sidewall. The radiator is disposed adjacent to the first sidewall of the air cavity. The director is disposed adjacent to the second sidewall of the air cavity.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ting Ruei CHEN, Hung-Hsiang CHENG, Guo-Cheng LIAO, Yun-Hsiang TIEN
  • Patent number: 11316249
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate having a first surface and a second surface opposite to the first surface, an antenna module disposed on the first surface of the first substrate, an electronic component module disposed on the first surface of the first substrate, and a first package body encapsulating the antenna module and the electronic component module. The antenna module has a first surface facing the first surface of the first substrate, a second surface opposite to the first surface of the antenna module, and a lateral surface extending between the first surface of the antenna module and the second surface of the antenna module. The lateral surface of the antenna module faces the electronic component module. A method of manufacturing a semiconductor device package is also provided.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 26, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hung-Hsiang Cheng
  • Patent number: 11239074
    Abstract: Devices comprising germanium nanosheets are described herein. Methods of forming such germanium nanosheets and devices including such germanium nanosheets are also described.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: February 1, 2022
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventor: Hung-Hsiang Cheng
  • Patent number: 11228088
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes an antenna layer having a feeding region and an insulating layer disposed on the antenna layer. The insulating layer has a first portion in contact with the antenna layer and a second portion on the first portion. The first portion and the second portion of the insulating layer define a stepped structure exposing the feeding region of the antenna layer. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: January 18, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hung-Hsiang Cheng
  • Publication number: 20210273315
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate having a first surface and a second surface opposite to the first surface, an antenna module disposed on the first surface of the first substrate, an electronic component module disposed on the first surface of the first substrate, and a first package body encapsulating the antenna module and the electronic component module. The antenna module has a first surface facing the first surface of the first substrate, a second surface opposite to the first surface of the antenna module, and a lateral surface extending between the first surface of the antenna module and the second surface of the antenna module. The lateral surface of the antenna module faces the electronic component module. A method of manufacturing a semiconductor device package is also provided.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hung-Hsiang CHENG
  • Publication number: 20210249756
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes an antenna layer having a feeding region and an insulating layer disposed on the antenna layer. The insulating layer has a first portion in contact with the antenna layer and a second portion on the first portion. The first portion and the second portion of the insulating layer define a stepped structure exposing the feeding region of the antenna layer. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 12, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hung-Hsiang CHENG
  • Patent number: 11031239
    Abstract: Devices comprising germanium nanosheets are described herein. Methods of forming such germanium nanosheets and devices including such germanium nanosheets are also described.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: June 8, 2021
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventor: Hung-Hsiang Cheng
  • Publication number: 20210036111
    Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.
    Type: Application
    Filed: October 5, 2020
    Publication date: February 4, 2021
    Inventors: Hung-Hsiang CHENG, Samuel C. PAN
  • Patent number: 10797137
    Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 6, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hung-Hsiang Cheng, Samuel C. Pan
  • Publication number: 20200051814
    Abstract: Devices comprising germanium nanosheets are described herein. Methods of forming such germanium nanosheets and devices including such germanium nanosheets are also described.
    Type: Application
    Filed: October 10, 2019
    Publication date: February 13, 2020
    Inventor: Hung-Hsiang Cheng
  • Publication number: 20200006067
    Abstract: Devices comprising germanium nanosheets are described herein. Methods of forming such germanium nanosheets and devices including such germanium nanosheets are also described.
    Type: Application
    Filed: May 9, 2019
    Publication date: January 2, 2020
    Inventor: Hung-Hsiang Cheng
  • Publication number: 20190006470
    Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.
    Type: Application
    Filed: April 27, 2018
    Publication date: January 3, 2019
    Inventors: Hung-Hsiang CHENG, Samuel C. PAN
  • Publication number: 20160044249
    Abstract: A network camera that connects a plurality of extensible imagers includes at least one imaging module and a camera body. The at least one imaging module includes a lens, an image sensor, an image digital signal processor with a video encoder and a USB connecting line. The camera body includes a plurality of USB ports for the USB signal line of the at least one imaging module to insert therein, a CPU and at least one signal output interface. The image sensor captures a digital image via the lens. The digital image is processed by the image digital signal processor and the video encoder and transmitted to the camera body via the USB connecting line. The digital image is further processed by computations of the CPU to form required signals outputted via the signal output interface.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 11, 2016
    Inventors: CI-FANG SYU, SHANG-FENG HUANG, CHENG-KANG TSENG, HUNG-HSIANG CHENG
  • Patent number: 8541883
    Abstract: The present invention relates to a semiconductor device having a shielding layer. The semiconductor device includes a substrate, an inner metal layer, a shielding layer, an insulation material, a metal layer, a passivation layer and a redistribution layer. The inner metal layer is disposed in a through hole of the substrate. The shielding layer surrounds the inner annular metal. The insulation material is disposed between the inner metal layer and the shielding layer. The metal layer is disposed on a surface of the substrate, contacts the shielding layer and does not contact the inner metal layer. The redistribution layer is disposed in an opening of the passivation layer so as to contact the inner metal layer.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: September 24, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hung-Hsiang Cheng, Tzu-Chih Lin, Chang-Ying Hung, Chih-Wei Wu
  • Publication number: 20130134601
    Abstract: The present invention relates to a semiconductor device having a shielding layer and a method for making the same. The semiconductor device includes a substrate, an inner metal layer, a shielding layer, an insulation material, a metal layer, a passivation layer and a redistribution layer. The inner metal layer is disposed in a through hole of the substrate. The shielding layer surrounds the inner annular metal. The insulation material is disposed between the inner metal layer and the shielding layer. The metal layer is disposed on a surface of the substrate, contacts the shielding layer and does not contact the inner metal layer. The redistribution layer is disposed in an opening of the passivation layer so as to contact the inner metal layer.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hung-Hsiang Cheng, Tzu-Chih Lin, Chang-Ying Hung, Chih-Wei Wu
  • Patent number: 8389394
    Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: March 5, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Yi Huang, Hung-Hsiang Cheng