Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

Abstract: The present invention relates to a circuit substrate having a first conductive layer. The first conductive layer includes at least one power/ground plane. The power/ground plane includes at least one plane edge and plurality of grid lines. Each grid line has a width. The grid lines intersect each other to define a plurality of first grid holes, wherein the distance between the first grid hole that is closest to the plane edge and the plane edge is 1.5 times the width. Thus, the influence on the resistance of power signal and ground signal caused by the first grid holes is reduced, power integrity is improved, and heat generation is reduced.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

Abstract: A semiconductor package and a method for making the same, whereby the semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, and second and third metal layers. The substrate has a surface having at least first and second pads. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

Abstract: A circuit board includes a plurality of signal lines and a plurality of shielding walls. The shield walls are disposed between the signal lines. Each shield wall includes an upper surface, a lower surface, a rectangular groove, a first metal layer and a second metal layer. The lower surface is opposite to the upper surface. The rectangular groove extends from the upper surface to the lower surface. The first metal layer is disposed on the upper surface. The second metal layer is disposed in the rectangular groove and electrically connected to the first metal layer.

Abstract: The present invention relates to a semiconductor device package having a chip with a conductive layer. The semiconductor device package includes a substrate, a chip, at least one first electrical connecting element and at least one second electrical connecting element. The substrate has a first surface and a first circuit layer. The first circuit layer is disposed adjacent to the first surface. The chip is attached to the substrate and has a surface, at least one first pad, a plurality of second pads and a conductive layer. The first pad, the second pads and the conductive layer are disposed adjacent to the surface, and the conductive layer connects the second pads. The first electrical connecting element and the second electrical connecting element electrically connect the substrate to the chip. Therefore, the conductive layer of the chip has the effects of controlling the characteristic impedance and increasing the signal integrity.

Abstract: Carrier with solid antenna structure comprises a substrate and at least one solid antenna structure. The substrate has an upper surface, a lower surface, at least one first slot communicating with the upper surface and the lower surface and at least one second slot communicating with the upper surface and the lower surface. The solid antenna structure has a dielectric block formed between the first slot and the second slot and a radiation conductor, in which the dielectric block encloses the radiation conductor. In this invention, the solid antenna structure is used to enable the carrier to be applied to higher power transmission. Additionally, by setting the material of the dielectric block and optimizing the size of the radiation conductor, the carrier can be applied to multi-band.

Abstract: The present invention relates to a substrate of a window ball grid array package and a method for making the same. The substrate includes a core layer, a first conductive layer, a second conductive layer, at least one window and at least one via. The window includes a first through hole and a third conductive layer. The first through hole penetrates the substrate and has a first sidewall. The third conductive layer is disposed on the first sidewall and connects the first conductive layer and the second conductive layer. The via includes a second through hole and a fourth conductive layer. The second through hole penetrates the substrate and has a second sidewall. The fourth conductive layer is disposed on the second sidewall and connects the first conductive layer and the second conductive layer. As a result, the substrate has the effect of controlling the characteristic impedance and increasing the signal integrity.

Abstract: The present invention relates to a substrate of a window ball grid array package. The substrate includes at least one window, a first conductive layer, a second conductive layer, a dielectric layer, a plurality of first vias and a plurality of second vias. The window penetrates the substrate. The first conductive layer has a plurality of fingers and at least one first power/ground plane, and the fingers are disposed at the periphery of the window. The second conductive layer has at least one second power/ground plane. The dielectric layer is disposed between the first conductive layer and the second conductive layer. The first vias electrically connect the first power/ground plane to the second power/ground plane. The second vias are disposed between the fingers and the window, and electrically connect some of the fingers to the second power/ground plane. Thus, the substrate can control the characteristic impedance and increase the signal integrity.

Abstract: The present invention relates to a substrate for a window ball grid array package. The substrate has at least one window, a plurality of fingers and at least one power/ground section (or power/ground ring). The window penetrates the substrate. The fingers are disposed at the periphery of the window. The power/ground section (or power/ground ring) is disposed between the fingers and the window. The power/ground section (or power/ground ring) is connected to a power/ground voltage so that the power/ground section (or power/ground ring) can improve the smoothness of the current and power integrity, and reduce the heat generation.

Abstract: The present invention relates to a circuit substrate having a first conductive layer. The first conductive layer includes at least one power/ground plane. The power/ground plane includes at least one plane edge and plurality of grid lines. Each grid line has a width. The grid lines intersect each other to define a plurality of first grid holes, wherein the distance between the first grid hole that is closest to the plane edge and the plane edge is 1.5 times the width. Thus, the influence on the resistance of power signal and ground signal caused by the first grid holes is reduced, power integrity is improved, and heat generation is reduced.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

Abstract: A method of cutting signal wire preserved on circuit board applicable to a circuit layout is provided to reduce signal return loss induced by the preserved wires. The circuit layout has a plurality of preserved wires and a common contact electrically connected to the preserved wires. The cutting method is performed by cutting off one of the preserved wires and disconnecting a break part of the wire from the common contact.

Abstract: Carrier with solid antenna structure comprises a substrate and at least one solid antenna structure. The substrate has an upper surface, a lower surface, at least one first slot communicating with the upper surface and the lower surface and at least one second slot communicating with the upper surface and the lower surface. The solid antenna structure has a dielectric block formed between the first slot and the second slot and a radiation conductor, in which the dielectric block encloses the radiation conductor. In this invention, the solid antenna structure is used to enable the carrier to be applied to higher power transmission. Additionally, by setting the material of the dielectric block and optimizing the size of the radiation conductor, the carrier can be applied to multi-band.

Abstract: The present invention relates to a semiconductor device having a passive device. The semiconductor device includes a substrate and at least one passive device. The substrate has at least one via. The via has at least two conductive elements therein. The conductive elements are not electrically connected to each other. The passive device has at least two electrodes, and is disposed on the substrate. The electrodes are electrically connected to the conductive elements respectively. The passive device needs only one via, so the amount of vias can be reduced effectively. In addition, the conductive path formed by the conductive elements and the passive device is relatively short, so that the inductance is lowered and the electrical performance is raised.

Abstract: A circuit board includes a plurality of signal lines and a plurality of shielding walls. The shield walls are disposed between the signal lines. Each shield wall includes an upper surface, a lower surface, a rectangular groove, a first metal layer and a second metal layer. The lower surface is opposite to the upper surface. The rectangular groove extends from the upper surface to the lower surface. The first metal layer is disposed on the upper surface. The second metal layer is disposed in the rectangular groove and electrically connected to the first metal layer.