Patents by Inventor Hung-I Su
Hung-I Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916141Abstract: A method for fabricating a shield gate MOSFET includes forming an epitaxial layer having a first conductivity type, forming a plurality of trenches in the epitaxial layer, forming a first and a second doped regions in the epitaxial layer at a bottom of each of the trenches, wherein the first doped region has a second conductivity type, and the second doped region has the first conductivity type. An insulating layer and a conductive layer as a shield gate are orderly formed in each of the trenches, and a portion of the conductive layer and the insulating layer are removed to expose a portion of the epitaxial layer in the trenches. An inter-gate oxide layer and a gate oxide layer are formed in the trenches, and a control gate is formed on the inter-gate oxide layer in the plurality of trenches.Type: GrantFiled: October 20, 2021Date of Patent: February 27, 2024Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Hung-I Su, Chang-Chin Ho, Yong-Kang Jiang
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Patent number: 11525668Abstract: A method of performing metrology analysis of a thin film includes coupling a radiation into an optical element disposed adjacent to a surface of the thin film. The radiation is coupled such that the radiation is totally internally reflected at an interface between the optical element and the thin film. An evanescent radiation generated at the interface penetrates the thin film. The method furthers include analyzing the evanescent radiation scattered by the thin film to obtain properties of the thin film.Type: GrantFiled: January 4, 2021Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ji-Feng Ying, Baohua Niu, David Hung-I Su
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Publication number: 20220045210Abstract: A method for fabricating a shield gate MOSFET includes forming an epitaxial layer having a first conductivity type, forming a plurality of trenches in the epitaxial layer, forming a first and a second doped regions in the epitaxial layer at a bottom of each of the trenches, wherein the first doped region has a second conductivity type, and the second doped region has the first conductivity type. An insulating layer and a conductive layer as a shield gate are orderly formed in each of the trenches, and a portion of the conductive layer and the insulating layer are removed to expose a portion of the epitaxial layer in the trenches. An inter-gate oxide layer and a gate oxide layer are formed in the trenches, and a control gate is formed on the inter-gate oxide layer in the plurality of trenches.Type: ApplicationFiled: October 20, 2021Publication date: February 10, 2022Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Hung-I Su, Chang-Chin Ho, Yong-Kang Jiang
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Publication number: 20210148695Abstract: A method of performing metrology analysis of a thin film includes coupling a radiation into an optical element disposed adjacent to a surface of the thin film. The radiation is coupled such that the radiation is totally internally reflected at an interface between the optical element and the thin film. An evanescent radiation generated at the interface penetrates the thin film. The method furthers include analyzing the evanescent radiation scattered by the thin film to obtain properties of the thin film.Type: ApplicationFiled: January 4, 2021Publication date: May 20, 2021Inventors: Ji-Feng YING, Baohua NIU, David Hung-I SU
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Publication number: 20210020778Abstract: A shield gate MOSFET includes an epitaxial layer having a first conductivity type, a plurality of trenches in the epitaxial layer, a shield gate disposed in the trenches, a control gate on the shield gate in the trenches, an insulating layer between the shield gate and the epitaxial layer, a gate oxide layer between the control gate and the epitaxial layer, an inter-gate oxide layer between the shield gate and the control gate, a first doped region in the epitaxial layer at the bottom of the trenches, and a second doped region between the bottom of the trenches and the first doped region. The first doped region has a second conductivity type, and the second doped region has the first conductivity type, and thus the leakage path may be reduced in the presence of the second doped region so as to improve breakdown voltage.Type: ApplicationFiled: October 25, 2019Publication date: January 21, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Hung-I Su, Chang-Chin Ho, Yong-Kang Jiang
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Patent number: 10883820Abstract: A method of performing metrology analysis of a thin film includes coupling a radiation into an optical element disposed adjacent to a surface of the thin film. The radiation is coupled such that the radiation is totally internally reflected at an interface between the optical element and the thin film. An evanescent radiation generated at the interface penetrates the thin film. The method furthers include analyzing the evanescent radiation scattered by the thin film to obtain properties of the thin film.Type: GrantFiled: February 28, 2018Date of Patent: January 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Baohua Niu, Ji-Feng Ying, David Hung-I Su
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Patent number: 10679820Abstract: A method includes applying a voltage to a wafer or a device under test (DUT). The wafer or the DUT is illuminated with an electron beam after applying the voltage to the wafer or the DUT. Cathodoluminescent light emitted from the wafer or the DUT in response to the electron beam is detected. One or more characteristics of the wafer or the DUT are determined based on the detected cathodoluminescent light.Type: GrantFiled: November 15, 2018Date of Patent: June 9, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bao-Hua Niu, Jung-Hsiang Chuang, David Hung-I Su
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Publication number: 20190145756Abstract: A method of performing metrology analysis of a thin film includes coupling a radiation into an optical element disposed adjacent to a surface of the thin film. The radiation is coupled such that the radiation is totally internally reflected at an interface between the optical element and the thin film. An evanescent radiation generated at the interface penetrates the thin film. The method furthers include analyzing the evanescent radiation scattered by the thin film to obtain properties of the thin film.Type: ApplicationFiled: February 28, 2018Publication date: May 16, 2019Inventors: Baohua NIU, Ji-Feng YING, David Hung-I SU
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Publication number: 20190103248Abstract: A method includes applying a voltage to a wafer or a device under test (DUT). The wafer or the DUT is illuminated with an electron beam after applying the voltage to the wafer or the DUT. Cathodoluminescent light emitted from the wafer or the DUT in response to the electron beam is detected. One or more characteristics of the wafer or the DUT are determined based on the detected cathodoluminescent light.Type: ApplicationFiled: November 15, 2018Publication date: April 4, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bao-Hua NIU, Jung-Hsiang CHUANG, David Hung-I SU
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Patent number: 10141158Abstract: A wafer and DUT inspection apparatus and a wafer and DUT inspection method using thereof are provided. The apparatus includes a vacuum chamber, a stage, an electron gun, a lens system, an optical mirror and a detector. In the vacuum chamber, the stage is disposed near a first end, and the electron gun is disposed near a second end opposite to the first end. The lens system disposed between the stage and the electron gun is a total reflective achromatic lens system including a first lens and a second lens. The second lens having a second aperture is disposed between the electron gun and the first lens having a first aperture aligned with the second aperture. The optical mirror is disposed between the lens system and the electron gun. The detector is horizontally aligned with the optical mirror and configured to detect cathodoluminescence reflected from the optical mirror.Type: GrantFiled: March 21, 2017Date of Patent: November 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bao-Hua Niu, Jung-Hsiang Chuang, David Hung-I Su
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Publication number: 20180158647Abstract: A wafer and DUT inspection apparatus and a wafer and DUT inspection method using thereof are provided. The apparatus includes a vacuum chamber, a stage, an electron gun, a lens system, an optical mirror and a detector. In the vacuum chamber, the stage is disposed near a first end, and the electron gun is disposed near a second end opposite to the first end. The lens system disposed between the stage and the electron gun is a total reflective achromatic lens system including a first lens and a second lens. The second lens having a second aperture is disposed between the electron gun and the first lens having a first aperture aligned with the second aperture. The optical mirror is disposed between the lens system and the electron gun. The detector is horizontally aligned with the optical mirror and configured to detect cathodoluminescence reflected from the optical mirror.Type: ApplicationFiled: March 21, 2017Publication date: June 7, 2018Inventors: Bao-Hua Niu, Jung-Hsiang Chuang, David Hung-I Su