SHIELD GATE MOSFET AND METHOD FOR FABRICATING THE SAME
A shield gate MOSFET includes an epitaxial layer having a first conductivity type, a plurality of trenches in the epitaxial layer, a shield gate disposed in the trenches, a control gate on the shield gate in the trenches, an insulating layer between the shield gate and the epitaxial layer, a gate oxide layer between the control gate and the epitaxial layer, an inter-gate oxide layer between the shield gate and the control gate, a first doped region in the epitaxial layer at the bottom of the trenches, and a second doped region between the bottom of the trenches and the first doped region. The first doped region has a second conductivity type, and the second doped region has the first conductivity type, and thus the leakage path may be reduced in the presence of the second doped region so as to improve breakdown voltage.
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This application claims the priority benefit of Taiwan application serial no. 108125082, filed on Jul. 16, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND Technical FieldThe disclosure relates to a semiconductor structure and a method for fabricating the same, and more particularly, to a shield gate MOSFET and a method for fabricating the same.
Description of Related ArtThe shield gate MOSFET is an improved structure of the trench gate MOS structure. Compared with the conventional MOS structure, the shield gate MOSFET may effectively reduce the capacitance of the gate to the drain (Cgd), thereby improving switching loss. With advancements in terminal consumer products, there is still a great need in related industries for novel semiconductor structures that may further improve the performance of various components.
However, as components get smaller and operating voltage is increased, there is a need to seek a technical solution to increase component breakdown voltage.
SUMMARY OF THE DISCLOSUREThe disclosure provides a shield gate MOSFET that may improve the drain-source breakdown voltage (BVDss).
The disclosure provides a method for fabricating a shield gate MOSFET, which may be integrated into an existing process to produce a shield gate MOSFET with high breakdown voltage.
A shield gate MOSFET of the disclosure includes an epitaxial layer having a first conductivity type, a plurality of trenches formed in the epitaxial layer, a shield gate disposed in the trenches, a control gate on the shield gate in the trenches, an insulating layer between the shield gate and the epitaxial layer, a gate oxide layer between the control gate and the epitaxial layer, an inter-gate oxide layer between the shield gate and the control gate, a first doped region in the epitaxial layer at the bottom of the trenches, and a second doped region between the bottom of the trenches and the first doped region. The first doped region has a second conductivity type, and the second doped region has the first conductivity type.
In an embodiment of the disclosure, the first conductivity type is N type and the second conductivity type is P type.
In an embodiment of the disclosure, the first conductivity type is P type and the second conductivity type is N type.
In an embodiment of the disclosure, a top surface of the shield gate covered by the inter-gate oxide layer has rounded corners.
In an embodiment of the disclosure, the shield gate MOSFET further includes a source region disposed on a surface of the epitaxial layer, and a doping concentration of the second doped region is less than a doping concentration of the source region.
In an embodiment of the disclosure, a doping concentration of the first doped region is a uniform concentration.
In an embodiment of the disclosure, the trenches may further extend to a connecting region of the epitaxial layer, the shield gate is extended into the trenches in the connecting region, and the shield gate MOSFET may further include a protruding portion in the trenches of the connecting region as a contact electrically connected to the shield gate.
In an embodiment of the disclosure, the control gate is not extended to the connecting region.
A method for fabricating a shield gate MOSFET of the disclosure includes the following steps. An epitaxial layer having a first conductivity type is formed. A plurality of trenches are formed in the epitaxial layer. A first doped region having a second conductivity type and a second doped region having the first conductivity type are sequentially formed in the epitaxial layer at a bottom of each trench. A MOSFET having a shield gate is formed in each trench.
In another embodiment of the disclosure, the first conductivity type is N type and the second conductivity type is P type.
In another embodiment of the disclosure, the first conductivity type is P type and the second conductivity type is N type.
In another embodiment of the disclosure, the steps of forming the MOSFET having the shield gate includes the following. An insulating layer is formed on a surface of the epitaxial layer in each trench. A conductive layer is formed on the insulating layer in each trench. A portion of the conductive layer is removed to form a shield gate and expose a portion of the insulating layer. The exposed insulating layer is removed. An inter-gate oxide layer and a gate oxide layer are formed in the trench, wherein the inter-gate oxide layer covers a top surface of the shield gate, and the inter-gate oxide layer covers the surface of the epitaxial layer. A control gate is formed on the inter-gate oxide layer in the trench.
In another embodiment of the disclosure, after the portion of the conductive layer is removed, the top surface of the shield gate may be further rounded.
In another embodiment of the disclosure, the fabricating method may further include forming a source region on the surface of the epitaxial layer, and a doping concentration of the second doped region is less than a doping concentration of the source region.
In another embodiment of the disclosure, a doping concentration of the first doped region is a uniform concentration.
In another embodiment of the disclosure, the epitaxial layer includes a connecting region, and thus when the trenches are formed, the trenches are also formed in the connecting region, and before the step of removing a portion of the conductive layer, a protective layer may be formed on the connecting region to keep the conductive layer in the connecting region.
Based on the above, in the disclosure, the first and second doped regions having different conductivity types are formed in the epitaxial layer at the bottom of the trenches, and therefore the first doped region having a different conductivity type than the epitaxial layer may provide a uniform field distribution, and the second doped region having the same conductivity type as the epitaxial layer is located between the first doped region and the bottom of the trenches to reduce leakage path, thereby improving drain-source breakdown voltage.
To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
The figures in the following embodiments are intended to more comprehensively describe the exemplary embodiments of the inventive concept, but the disclosure may still be implemented in many different forms, and the disclosure should not be construed as limited to the recited embodiments. In the figures, for clarity, the relative thickness and location of film layers, regions, and/or structural elements may be reduced or enlarged. Moreover, in the present specification, “first”, “second”, “third” . . . etc. are used to describe different regions, film layers, and/or blocks, but such terms are only intended to differentiate a region, film layer, or block from another region, film layer, or block. Therefore, a first region, film layer, or block discussed below may be referred to as a second region, film layer, or block without compromising the teaching of the embodiments. Moreover, the same or similar reference numerals represent the same or similar devices and are not repeated in the following paragraphs.
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Next, in order to form a MOSFET having a shield gate in each trench 302, the following process may be performed, but the scope of the disclosure is not limited to the following steps. Depending on design requirements, there may be additional steps or some steps omitted.
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Several experiments are described below to prove the efficacy of the disclosure. However, the scope of the disclosure is not limited to the following experimental content.
SIMULATION EXPERIMENTAL EXAMPLE 1The simulated structure is the shield gate MOSFET (EPI resistance is 0.35 Ω·cm/thickness 4 μm) shown in
As may be seen from
The simulation was carried out in the same manner as in simulation experimental example 1, but there was no second doped region. That is to say, for example, the trench bottom in
It may be seen from Table 1 that the overall breakdown voltage would be reduced to 143 V or less in the absence of the second doped region.
Based on the above, in the disclosure, first and second doped regions having different conductivity types are formed in the epitaxial layer at the bottom of the shield gate MOSFET, second doped regions having the same conductivity type as the epitaxial layer are in direct contact with the trench bottom, and first doped regions having different conductivity types from the epitaxial layer provide a uniform field distribution below. Therefore, the leakage path of the device may be reduced by the second doped regions, thereby improving drain-source breakdown voltage.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.
Claims
1. A shield gate MOSFET, comprising:
- an epitaxial layer having a first conductivity type;
- a plurality of trenches formed in the epitaxial layer;
- a shield gate disposed in the plurality of trenches;
- a control gate disposed on the shield gate in the plurality of trenches;
- an insulating layer disposed between the shield gate and the epitaxial layer;
- a gate oxide layer disposed between the control gate and the epitaxial layer;
- an inter-gate oxide layer disposed between the shield gate and the control gate; and
- a first doped region and a second doped region disposed in the epitaxial layer at a bottom of the trenches, and the second doped region is located between the shield gate and the first doped region, wherein the first doped region has a second conductivity type, and the second doped region has the first conductivity type.
2. The shield gate MOSFET of claim 1, wherein the first conductivity type is N type and the second conductivity type is P type.
3. The shield gate MOSFET of claim 1, wherein the first conductivity type is P type and the second conductivity type is N type.
4. The shield gate MOSFET of claim 1, wherein a top surface of the shield gate covered by the inter-gate oxide layer has rounded corners.
5. The shield gate MOSFET of claim 1, further comprising a source region disposed on a surface of the epitaxial layer, and a doping concentration of the second doped region is less than a doping concentration of the source region.
6. The shield gate MOSFET of claim 1, wherein a doping concentration of the first doped region is a uniform concentration.
7. The shield gate MOSFET of claim 1, wherein the plurality of trenches further extends to a connecting region of the epitaxial layer, the shield gate is extended into the plurality of trenches in the connecting region, and the shield gate MOSFET further comprises a protruding portion in the trenches of the connecting region as a contact electrically connected to the shield gate.
8. The shield gate MOSFET of claim 7, wherein the control gate is not extended to the connecting region.
9. A method for fabricating a shield gate MOSFET, comprising:
- forming an epitaxial layer, wherein the epitaxial layer has a first conductivity type;
- forming a plurality of trenches in the epitaxial layer;
- forming a first doped region and a second doped region in the epitaxial layer at a bottom of each of the trenches, wherein the first doped region has a second conductivity type, and the second doped region has the first conductivity type; and
- forming a MOSFET having a shield gate in each of the trenches.
10. The method for fabricating the shield gate MOSFET of claim 9, wherein the first conductivity type is N type and the second conductivity type is P type.
11. The method for fabricating the shield gate MOSFET of claim 9, wherein the first conductivity type is P type and the second conductivity type is N type.
12. The method for fabricating the shield gate MOSFET of claim 9, wherein the step of forming the MOSFET having the shield gate comprises:
- forming an insulating layer on a surface of the epitaxial layer in each of the trenches;
- forming a conductive layer on the insulating layer in each of the trenches;
- removing a portion of the conductive layer to form the shield gate and expose a portion of the insulating layer;
- removing the exposed insulating layer;
- forming an inter-gate oxide layer and a gate oxide layer in the trenches, wherein the inter-gate oxide layer covers a top surface of the shield gate, and the gate oxide layer covers a surface of the epitaxial layer; and
- forming a control gate on the inter-gate oxide layer in the plurality of trenches.
13. The method for fabricating the shield gate MOSFET of claim 12, further comprising, after removing the portion of the conductive layer and the exposed insulating layer: rounding the top surface of the shield gate.
14. The method for fabricating the shield gate MOSFET of claim 9, further comprising forming a source region on a surface of the epitaxial layer, and a doping concentration of the second doped region is less than a doping concentration of the source region.
15. The method for fabricating the shield gate MOSFET of claim 9, wherein a doping concentration of the first doped region is a uniform concentration.
16. The method for fabricating the shield gate MOSFET of claim 12, wherein the epitaxial layer comprises a connecting region, and when the plurality of trenches are formed in the epitaxial layer, the plurality of trenches are extended to the connecting region, and before the step of removing the portion of the conductive layer, a protective layer is formed on the connecting region to keep the conductive layer in the connecting region.
Type: Application
Filed: Oct 25, 2019
Publication Date: Jan 21, 2021
Applicant: Powerchip Semiconductor Manufacturing Corporation (Hsinchu)
Inventors: Hung-I Su (Hsinchu City), Chang-Chin Ho (Hsinchu City), Yong-Kang Jiang (Hsinchu City)
Application Number: 16/663,365