Patents by Inventor Hung-Jui Chang
Hung-Jui Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190006231Abstract: An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening.Type: ApplicationFiled: February 1, 2018Publication date: January 3, 2019Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Hung Jui Chang, Li-Te Hsu
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Publication number: 20180337090Abstract: Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.Type: ApplicationFiled: July 18, 2017Publication date: November 22, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: BO-JHIH SHEN, YI-WEI CHIU, HUNG JUI CHANG
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Publication number: 20180315648Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: ApplicationFiled: October 5, 2017Publication date: November 1, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Allen KE, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
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Publication number: 20180166321Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having reduced trench loading effect. The present disclosure provides a novel multi-layer cap film incorporating one or more oxygen-based layers for reducing trench loading effects in semiconductor devices. The multi-layer cap film can be made of a metal hard mask layer and one or more oxygen-based layers. The metal hard mask layer can be formed of titanium nitride (TiN). The oxygen-based layer can be formed of tetraethyl orthosilicate (TEOS).Type: ApplicationFiled: August 8, 2017Publication date: June 14, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Kai SUN, Yi-Wei Chiu, Hung Jui Chang, Chia-Ching Tsai
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Publication number: 20180151335Abstract: A plasma processing apparatus is provided. The apparatus includes a lower sheltering module. The apparatus further includes an upper sheltering module arranged adjacent to the lower sheltering module. The apparatus includes an upper plate and an upper PEZ ring positioned around the upper plate. The apparatus also includes a shadowing unit that includes a number of engaging parts in the form of arcs detachably positioned on the upper PEZ ring. In addition, the apparatus includes a plasma generation module for generating plasma in the peripheral region of the lower sheltering module and the upper sheltering module.Type: ApplicationFiled: May 11, 2017Publication date: May 31, 2018Inventors: Chun-Hsing WU, Hung-Jui CHANG, Chih-Ching CHENG, Yi-Wei CHIU, Kun-Cheng CHEN
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Publication number: 20180151334Abstract: A semiconductor manufacturing method and semiconductor manufacturing tool for performing the same are disclosed. The semiconductor manufacturing tool includes a plasma chamber, a mounting platform disposed within the plasma chamber, a focus ring disposed within the plasma chamber, and at least one actuator mechanically coupled to the focus ring and configured to move the focus ring vertically. The actuator is configured to move the focus ring vertically when a plasma is present in the plasma chamber.Type: ApplicationFiled: November 29, 2016Publication date: May 31, 2018Inventors: Yu-Chi Lin, Yi-Wei Chiu, Hung Jui Chang, Chin-Hsing Lin
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Patent number: 9982340Abstract: An apparatus comprises: a shower head having a supply plenum for supplying the gas to the chamber and a vacuum manifold fluidly coupled to the supply plenum; and at least one vacuum system fluidly coupled to the vacuum manifold of the shower head.Type: GrantFiled: April 4, 2012Date of Patent: May 29, 2018Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Chih-Tsung Lee, Hung Jui Chang, You-Hua Chou, Shiu-Ko Jangjian, Chung-En Kao, Ming-Chin Tsai, Huan-Wen Lai
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Publication number: 20170191869Abstract: A light sensor for sensing an illumination of a partial area is disclosed. The light sensor includes a first case, a second case, a first light absorption layer and at least one sensing module. The first case includes at least one hole. The at least one hole includes an axis. The second case is fastened to the first case, and a containing space is formed between the first case and the second case. The first light absorption layer is located on the first case. The at least one sensing module is located in the containing space, and the position of the at least one sensing module is located on the axis of the hole. The at least one sensing module is used for sensing the light from the partial area which passes through the hole so as to obtain the illumination of the partial area.Type: ApplicationFiled: December 2, 2016Publication date: July 6, 2017Inventors: CHIEH-HSIN KUO, HUNG-JUI CHANG, TING-FU HSU, WEI-CHE LEE
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Patent number: 9691809Abstract: Disclosed is a method of fabricating an image sensor device, such as a BSI image sensor, and more particularly, a method of forming a dielectric film in a radiation-absorption region without using a conventional plasma etching causing roughness on the surface and non-uniformity within a die and a wafer. The method includes providing layers comprising a substrate having radiation sensors adjacent its front surface, an anti-reflective layer formed over the back surface of the substrate, a sacrificial dielectric layer formed over the anti-reflective layer, and a conductive layer formed over the sacrificial dielectric layer in a radiation-blocking region. The method further includes removing the sacrificial dielectric layer in the radiation-absorption region completely by a highly selective etching process and forming a dielectric film on the anti-reflective layer by deposition such as CVD or PVD while precisely controlling the thickness.Type: GrantFiled: June 28, 2013Date of Patent: June 27, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeng Chang Her, Hung Jui Chang, Li Te Hsu, Chung-Bin Tseng
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Patent number: 9484207Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a wafer having a central portion and a peripheral portion surrounding the central portion. The method includes forming a first dielectric layer over the central portion. The first dielectric layer has first contact openings exposing conductive regions of the wafer. The method includes forming a protective layer over the peripheral portion. The method includes after forming the protective layer, performing a metal silicide process to form metal silicide structures over the conductive regions of the wafer.Type: GrantFiled: May 30, 2014Date of Patent: November 1, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jeng-Chang Her, Chia-Cheng Lin, Hung-Jui Chang, Yu-Sheng Su, Shu-Huei Suen
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Patent number: 9368394Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a semiconductor substrate; forming a conductive region at least partially in the semiconductor substrate; forming a dielectric layer over the substrate; forming a hard mask over the dielectric layer, the hard mask having an opening over the conductive region; dry etching the dielectric layer by a first etching gas to form a recessed feature, wherein a surface of the conductive region is therefore exposed at a bottom of the recessed feature, and a byproduct film is formed at an inner surface of the recessed feature; and dry etching the dielectric layer by a second etching gas, wherein the second etching gas chemically reacts with the byproduct film and the conductive region, and a sacrificial layer is therefore built up around the bottom of the recessed feature.Type: GrantFiled: March 31, 2015Date of Patent: June 14, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Li Hung, Te-Ming Kung, Chih-Hao Chen, Kei-Wei Chen, Ying-Lang Wang, Hung Jui Chang, Horng-Huei Tseng
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Publication number: 20150348838Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a wafer having a central portion and a peripheral portion surrounding the central portion. The method includes forming a first dielectric layer over the central portion. The first dielectric layer has first contact openings exposing conductive regions of the wafer. The method includes forming a protective layer over the peripheral portion. The method includes after forming the protective layer, performing a metal silicide process to form metal silicide structures over the conductive regions of the wafer.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Jeng-Chang HER, Chia-Cheng LIN, Hung-Jui CHANG, Yu-Sheng SU, Shu-Huei SUEN
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Patent number: 9196973Abstract: Disclosed are a solar junction box and a wire connecting structure of the solar junction box. The solar junction box includes plural first conductive tongues separately and perpendicularly plugged onto a printed circuit board, plural solar panel conducting plates combined to the first conductive tongues, and each solar panel conducting plate including an extension plate connected to a solar panel and a U-shaped snap-in plate bent and extended from the extension plate, and each U-shaped snap-in plate being snapped onto each first conductive tongue, plural insulators sheathed on the solar panel conducting plates, a pair of second conductive tongues separately and flatly attached onto a side of the printed circuit board, and two conducting terminals electrically connected to the pair of second conductive tongues. With the installation of the wire connecting structure, the volume of the solar junction box can be reduced to provide a stable electrical connection.Type: GrantFiled: March 6, 2014Date of Patent: November 24, 2015Assignee: CHICONY POWER TECHNOLOGY CO., LTD.Inventors: Hung-Jui Chang, Yu-Jen Lai
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Publication number: 20150296636Abstract: An electronic apparatus for a solar power system includes a first shell, a waterproof member, and a second shell. The first shell has a surrounding plate, a receiving space formed in the surrounding plate, and at least one clasp portion disposed on an inner side of the surrounding plate. A surrounding notch is formed on the top of the surrounding plate. The waterproof member is filled in the surrounding notch. The second shell has a surrounding protrusion and at least one clasp part disposed on an inner side of the surrounding protrusion. The clasp part snap fits the clasp portion correspondingly to make the surrounding protrusion embedded in the surrounding notch such that the waterproof member is clamped between the surrounding protrusion and the surrounding plate. Thus, waterproof and dustproof of the electronic apparatus are improved.Type: ApplicationFiled: April 11, 2014Publication date: October 15, 2015Applicant: Chicony Power Technology Co., Ltd.Inventors: Ying-Shiang WANG, Hung-Jui CHANG, Yu-Jen LAI
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Publication number: 20150255889Abstract: Disclosed are a solar junction box and a wire connecting structure of the solar junction box. The solar junction box includes plural first conductive tongues separately and perpendicularly plugged onto a printed circuit board, plural solar panel conducting plates combined to the first conductive tongues, and each solar panel conducting plate including an extension plate connected to a solar panel and a U-shaped snap-in plate bent and extended from the extension plate, and each U-shaped snap-in plate being snapped onto each first conductive tongue, plural insulators sheathed on the solar panel conducting plates, a pair of second conductive tongues separately and flatly attached onto a side of the printed circuit board, and two conducting terminals electrically connected to the pair of second conductive tongues. With the installation of the wire connecting structure, the volume of the solar junction box can be reduced to provide a stable electrical connection.Type: ApplicationFiled: March 6, 2014Publication date: September 10, 2015Applicant: Chicony Power Technology Co., Ltd.Inventors: Hung-Jui CHANG, Yu-Jen LAI
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Publication number: 20150003021Abstract: An inverter module converts a DC current generated by a photovoltaic panel to an AC current. The inverter module includes a housing and a PCB. The housing has a through hole. The PCB is received within the housing. An inverter circuit and a connection circuit are welded on a side of the PCB. The connection circuit includes a plurality of conductive terminals and a plurality of diodes. The conductive terminals are arranged in a row and adjacent to the through hole. Each of the conductive terminals is electrically connected to the inverter circuit. Each of the diodes is disposed between and electrically connected to the two neighboring conductive terminals thereof. By means of the integration of the inverter circuit, conductive terminals, and diodes, the space occupied by the inverter module can be reduced.Type: ApplicationFiled: June 29, 2013Publication date: January 1, 2015Inventor: Hung-Jui CHANG
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Publication number: 20140263958Abstract: Disclosed is a method of fabricating an image sensor device, such as a BSI image sensor, and more particularly, a method of forming a dielectric film in a radiation-absorption region without using a conventional plasma etching causing roughness on the surface and non-uniformity within a die and a wafer. The method includes providing layers comprising a substrate having radiation sensors adjacent its front surface, an anti-reflective layer formed over the back surface of the substrate, a sacrificial dielectric layer formed over the anti-reflective layer, and a conductive layer formed over the sacrificial dielectric layer in a radiation-blocking region. The method further includes removing the sacrificial dielectric layer in the radiation-absorption region completely by a highly selective etching process and forming a dielectric film on the anti-reflective layer by deposition such as CVD or PVD while precisely controlling the thickness.Type: ApplicationFiled: June 28, 2013Publication date: September 18, 2014Inventors: Jeng Chang Her, Hung Jui Chang, Li Te Hsu, Chung-Bin Tseng
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Patent number: 8624394Abstract: A semiconductor device includes a semiconductor body and a low K dielectric layer overlying the semiconductor body. A first portion of the low K dielectric layer comprises a dielectric material, and a second portion of the low K dielectric layer comprise an air gap, wherein the first portion and the second portion are laterally disposed with respect to one another. A method for forming a low K dielectric layer is also disclosed and includes forming a dielectric layer over a semiconductor body, forming a plurality of air gaps laterally disposed from one another in the dielectric layer, and forming a capping layer over the dielectric layer and air gaps.Type: GrantFiled: December 7, 2011Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung Jui Chang, Chih-Tsung Lee, You-Hua Chou, Shiu-Ko Jang Jian, Ming-Shiou Kuo
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Publication number: 20130267045Abstract: An apparatus comprises: a shower head having a supply plenum for supplying the gas to the chamber and a vacuum manifold fluidly coupled to the supply plenum; and at least one vacuum system fluidly coupled to the vacuum manifold of the shower head.Type: ApplicationFiled: April 4, 2012Publication date: October 10, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Tsung LEE, Hung Jui CHANG, You-Hua CHOU, Shiu-Ko JANGJIAN, Chung-En KAO, Ming-Chin TSAI, Huan-Wen LAI
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Patent number: 8497183Abstract: A method of making a device. The method comprises providing a first layer including a first material on a surface of a substrate, removing a portion of the first layer and a corresponding portion of the substrate to form an opening in the first layer and a recessed portion in the surface of the substrate, and supplying a liquid mixture to the opening and the recessed portion. The liquid mixture includes a first component having a first chemical affinity to the first material and a second component having a second chemical affinity to the first material, which is smaller than the first chemical affinity. The method also includes removing the second component and forming a second layer including the first component. The second layer covers the recessed portion and adheres to an edge portion of the first layer, such that the second layer and the recessed portion define a cavity.Type: GrantFiled: April 28, 2010Date of Patent: July 30, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: You-Hua Chou, Hsiang Hsiang Ko, Hung Jui Chang, Yi Ming Chen, Hsien-Wei Lin