Patents by Inventor Hung-Li Chiang
Hung-Li Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240155954Abstract: An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.Type: ApplicationFiled: January 16, 2024Publication date: May 9, 2024Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Lain-Jong Li
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Publication number: 20240145569Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yee-Chia YEO, Sung-Li WANG, Chi On CHUI, Jyh-Cherng SHEU, Hung-Li CHIANG, I-Sheng CHEN
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Patent number: 11967375Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.Type: GrantFiled: November 18, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Yu-Sheng Chen, Hon-Sum Philip Wong
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Publication number: 20240130100Abstract: A memory device is provided. The memory device includes a write pass-gate transistor, a read pass-gate transistor, a write word line, and a read word line. The write pass-gate transistor is disposed in a first layer. The read pass-gate transistor is disposed in a second layer above the first layer. The write word line is disposed in a metallization layer above the first layer and electrically coupled to the write pass-gate transistor through a write path. The read word line is disposed in the metallization layer and electrically coupled to the read pass-gate transistor through a read path. The write path is different from the read path.Type: ApplicationFiled: February 1, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Li Chiang, Jer-Fu Wang, Yi-Tse Hung, Chao-Ching Cheng, Iuliana Radu
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Patent number: 11963369Abstract: The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.Type: GrantFiled: July 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Li Chiang, Chao-Ching Cheng, Jung-Piao Chiu, Tzu-Chiang Chen, Yu-Sheng Chen
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Patent number: 11955554Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.Type: GrantFiled: July 15, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu, Ying-Keung Leung
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Publication number: 20240113197Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes a substrate and a gate structure. The substrate includes a fin. The fin includes a source region and a drain region spaced apart from the source region. The gate structure is located between the source region and the drain region. The gate structure includes a work function layer. The work function layer includes a compound of a metal material and a Group VIA material.Type: ApplicationFiled: January 16, 2023Publication date: April 4, 2024Inventors: JER-FU WANG, CHAO-CHING CHENG, HUNG-LI CHIANG, IULIANA RADU
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Publication number: 20240105515Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.Type: ApplicationFiled: November 28, 2023Publication date: March 28, 2024Inventors: Chao-Ching Cheng, Tzu-Ang Chao, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li
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Publication number: 20240088267Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yi PENG, Chih Chieh YEH, Chih-Sheng CHANG, Hung-Li CHIANG, Hung-Ming CHEN, Yee-Chia YEO
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Patent number: 11929115Abstract: A memory device and an operation method thereof are provided. The memory device includes memory cells, each having a static random access memory (SRAM) cell and a non-volatile memory cell. The SRAM cell is configured to store complementary data at first and second storage nodes. The non-volatile memory cell is configured to replicate and retain the complementary data before the SRAM cell loses power supply, and to rewrite the replicated data to the first and second storage nodes of the SRAM cell after the power supply of the SRAM cell is restored.Type: GrantFiled: April 8, 2022Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jer-Fu Wang, Hung-Li Chiang, Yi-Tse Hung, Tzu-Chiang Chen, Meng-Fan Chang
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Patent number: 11923413Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.Type: GrantFiled: February 7, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
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Publication number: 20240071834Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Li CHIANG, Chih-Liang CHEN, Tzu-Chiang CHEN, I-Sheng CHEN, Lei-Chun CHOU
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Patent number: 11910732Abstract: An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.Type: GrantFiled: May 23, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Lain-Jong Li
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Patent number: 11903334Abstract: A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.Type: GrantFiled: July 9, 2021Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Li Chiang, Jer-Fu Wang, Chao-Ching Cheng, Tzu-Chiang Chen
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Publication number: 20240047526Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate and spaced apart from each other in a first direction. The semiconductor structure further includes a gate structure wrapping around the nanostructures and a semiconductor layer attached to the nanostructures in a second direction different from the first direction. The semiconductor structure further includes inner spacers sandwiched between the semiconductor layer and the gate structure in the second direction and a silicide layer formed over the semiconductor layer. In addition, a first portion of the semiconductor layer is sandwiched between the inner spacers and the silicide layer in the second direction.Type: ApplicationFiled: October 16, 2023Publication date: February 8, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Ching CHENG, I-Sheng CHEN, Tzu-Chiang CHEN, Shih-Syuan HUANG, Hung-Li CHIANG
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Patent number: 11894438Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.Type: GrantFiled: June 21, 2021Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yee-Chia Yeo, Sung-Li Wang, Chi On Chui, Jyh-Cherng Sheu, Hung-Li Chiang, I-Sheng Chen
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Publication number: 20240032309Abstract: A memory device includes a first electrode, a selector layer and a plurality of first work function layers. The first work function layers are disposed between the first electrode and the selector layer, and a work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.Type: ApplicationFiled: October 3, 2023Publication date: January 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Yu-Sheng Chen, Xinyu BAO
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Publication number: 20240021226Abstract: In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.Type: ApplicationFiled: July 12, 2022Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
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Patent number: 11855187Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.Type: GrantFiled: October 11, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Chih-Sheng Chang, Hung-Li Chiang, Hung-Ming Chen, Yee-Chia Yeo
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Patent number: 11854895Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.Type: GrantFiled: July 20, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Ching Cheng, Tzu-Ang Chao, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li