Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

Abstract: Semiconductor structures and formation processes thereof are provided. A semiconductor structure of the present disclosure includes a semiconductor substrate, a plurality of transistors disposed on the semiconductor substrate and comprising a plurality of gate structures extending lengthwise along a first direction, a metallization layer disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias, a dielectric layer over the metallization layer, a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer, a semiconductor layer disposed conformally over the plurality of dielectric fins, a source contact and a drain contact disposed directly on the semiconductor layer, and a gate structure disposed over the semiconductor layer and between the source contact and the drain contact.

Abstract: In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.

Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a substrate, complex two-dimensional material layers disposed over the substrate, a gate structure and source and drain regions. The complex two-dimensional material layers are arranged spaced apart from one each other and in parallel to one another. The gate structure is disposed across and wraps around and surrounds first portions of the complex two-dimensional material layers. The source and drain regions are disposed on opposite sides of the gate structure and wrap around and surround second portions of the complex two-dimensional material layers.

Abstract: A memory device includes a first electrode, a selector layer and a plurality of first work function layers. The first work function layers are disposed between the first electrode and the selector layer, and a work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.

Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.

Abstract: One aspect of the present disclosure pertains to a device. The device includes a substrate, a logic circuit disposed on the substrate, and a nanoelectromechanical systems (NEMS) device electrically connected to the logic circuit and formed on the substrate. The NEMS device includes a first electrode electrically connected to the logic circuit, a second electrode electrically connected to a first power supply, a movable feature electrically connected to the second electrode, and a control electrode operable to move the movable feature relative to the first electrode.

Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.

Abstract: A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

Abstract: A method includes forming first bonding pads over a first substrate, wherein the first bonding pads include a layer of ferromagnetic material, wherein each first bonding pad produces a respective magnetic field having a first orientation; and bonding second bonding pads to the first bonding pads using metal-to-metal bonding.

Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and multiple nanostructures over the substrate. The semiconductor device structure also includes a semiconductor structure over the substrate, and topmost surfaces of the semiconductor structure and the nanostructures are at different height levels. The semiconductor device structure further includes an isolation structure surrounding a lower portion of the semiconductor structure and a gate stack wrapped around the nanostructures. The gate stack includes a gate dielectric layer, and the gate dielectric layer is continuously wrapped around a bottommost nanostructure of the nanostructures and extending along a top surface of the isolation structure.

Abstract: A memory cell includes a write access transistor, a storage transistor, and a read access transistor. A gate of the write access transistor is connected to a write word line, a source of the write access transistor is connected to a write bit line, and a drain of the write access transistor is connected to a gate of the storage transistor. A source of the storage transistor is connected to a source line and a drain of the storage transistor is connected to a source of the read access transistor. A gate of the read access transistor is connected to a read bit line and a drain of the read access transistor is connected to read bit line. The memory cell further includes a capacitive element having a first connection to the gate of the storage transistor and a second connection to a reference voltage source.

Abstract: An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.

Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

Abstract: A resistive memory device includes a bottom electrode, a switching layer including a first horizontal portion, a second horizontal portion over an upper surface of the bottom electrode, and a first vertical portion over a side surface of the bottom electrode, a top electrode including a first horizontal portion over the first horizontal portion of the switching layer, a second horizontal portion over the second horizontal portion of the switching layer, and a first vertical portion over the first vertical portion of the switching layer, and a conductive via contacting the first horizontal portion, the second horizontal portion and the first vertical portion of the top electrode. By providing a switching layer and a top electrode which conform to a non-planar profile of the bottom electrode, charge crowding and a localized increase in electric field may facilitate resistance-state switching and provide a reduced operating voltage.

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.

Abstract: An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.