Abstract: An illumination system, a projection apparatus and an illumination control method are provided. The illumination system includes an excitation light source, an optical component, a light source driver, a temperature sensing module and a controller. The excitation light source emits an excitation light beam. The optical component is located on a transmission path of the excitation light beam. The light source driver is configured to drive the excitation light source. The temperature sensing module is located in a neighboring region of the optical component and configured to sense a temperature of the neighboring region of the optical component to output a sensing voltage. The controller is configured to receive the sensing voltage to determine whether the sensing voltage falls out of a predetermined voltage range and configured to output a control signal to the light source driver to adjust the excitation light beam.

Abstract: A non-volatile memory cell is disclosed. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer over the substrate; a floating gate over the first oxide layer; a second oxide layer over the floating gate; and a control gate at least partially over the second oxide layer. At least one of the first oxide layer and the second oxide layer comprises fluorine.

Abstract: A projection device, a light source system and a projection method thereof are provided. A portion of the light-emitting units are controlled to provide a light beam as the first light beam. It is detected whether characteristic parameters of the light-emitting units providing the light beam reach a preset value. When the preset value is not reached, the light-emitting units providing the light beam are disabled, and the remaining light-emitting units are controlled to provide the back-up light beam as the first light beam. A portion of the first light beam is converted into a second light beam. The first light beam of which the wavelength is not converted and the second light beam are combined to generate an illumination beam. The illumination beam is converted into an image beam. The image beam is converted into a projection beam.

Abstract: A non-volatile memory cell is disclosed. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer over the substrate; a floating gate over the first oxide layer; a second oxide layer over the floating gate; and a control gate at least partially over the second oxide layer. At least one of the first oxide layer and the second oxide layer comprises fluorine.

Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.

Abstract: A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and electrically coupled in series, where the transistors comprise a floating gate. An interconnect structure overlies the pair of transistors. A shield is arranged in the interconnect structure, directly over the floating gate. The shield is configured to block ions in the interconnect structure from moving to the floating gate. A method for manufacturing an OTP memory cell with floating gate shielding is also provided.

Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.

Abstract: A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and electrically coupled in series, where the transistors comprise a floating gate. An interconnect structure overlies the pair of transistors. A shield is arranged in the interconnect structure, directly over the floating gate. The shield is configured to block ions in the interconnect structure from moving to the floating gate.

Abstract: A method for managing IM services and an electronic device using the same are provided. The method includes determining whether identification information respectively recorded in a first electronic device and a second electronic device is consistent when the first electronic device and the second electronic device are connected to each other through a network. The method also includes transmitting, by the second electronic device, at least one IM login information stored therein to the first electronic device if the identification information respectively recorded in the first electronic device and the second electronic device is consistent. The method further includes when a function button corresponding to a login function of the first electronic device receives a selection operation, executing, by the first electronic device, an IM service login procedure by using the at least one IM login information received from the second electronic device.

Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.

Abstract: A method for receiving an optical orthogonal frequency-division multiplexing (OFDM) signal and a receiver thereof are applicable to an optical OFDM system. The receiving method includes the following steps. An optical signal is converted into a digital signal. A symbol boundary of the digital signal is estimated. A guard interval of the digital signal is removed according to the symbol boundary, so as to generate an electrical signal. The electrical signal is converted into a plurality of frequency domain sub-carriers in a fast Fourier transform (FFT) manner. A timing offset is estimated with pilot carriers and frequency domain sub-carriers corresponding to the same symbol period. The estimated symbol boundary is compensated with the timing offset. Each frequency domain sub-carrier includes a plurality of pilot carrier signals. Through the receiving method, the timing offset arisen from chromatic dispersion of an optical fiber is effectively estimated and adopted for compensation.

Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.

Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.

Abstract: An integrated circuit structure includes a semiconductor substrate; a first titanium layer over the semiconductor substrate, wherein the first titanium layer has a first thickness less than 130 ?; a first titanium nitride layer over and contacting the first titanium layer; and an aluminum-containing layer over and contacting the first titanium nitride layer.

Abstract: A method for receiving an optical orthogonal frequency-division multiplexing (OFDM) signal and a receiver thereof are applicable to an optical OFDM system. The receiving method includes the following steps. An optical signal is converted into a digital signal. A symbol boundary of the digital signal is estimated. A guard interval of the digital signal is removed according to the symbol boundary, so as to generate an electrical signal. The electrical signal is converted into a plurality of frequency domain sub-carriers in a fast Fourier transform (FFT) manner. A timing offset is estimated with pilot carriers and frequency domain sub-carriers corresponding to the same symbol period. The estimated symbol boundary is compensated with the timing offset. Each frequency domain sub-carrier includes a plurality of pilot carrier signals. Through the receiving method, the timing offset arisen from chromatic dispersion of an optical fiber is effectively estimated and adopted for compensation.

Abstract: An FFT processor is disclosed, which includes a first multi-pipelined MDC unit, a second multi-pipelined MDC unit and a switching network. The first multi-pipelined MDC unit and the second multi-pipelined MDC unit respectively employ a plurality of MDC circuits to change the positions of the delayers thereof in parallel way. By changing the operation time sequence of the signals in the first multi-pipelined MDC unit and the second multi-pipelined MDC unit, the first multi-pipelined MDC unit is able to directly send the operation results to the second multi-pipelined MDC unit through the switching network.

Abstract: A fermentation apparatus includes a fermentation tank, an air-hole mesh board, a lift-up cover, a blender and a pressurization equipment. An opening is above fermentation tank, an oblique-board base is at the bottom of the fermentation tank, and a feed opening and an air outlet are on the fermentation tank. Two air inlet holes are on the oblique-board base to form a passage through the oblique-board base. Exhaustion holes are on a surface of the oblique-board base and interconnected with the passage. The air-hole mesh board is installed in the fermentation tank and between the feed opening and the oblique-board base. The lift-up cover is connected to the fermentation tank and disposed above the fermentation tank for covering the opening. The blender is between the lift-up cover and the air-hole mesh board. The pressurization equipment is connected to the air inlet hole for supplying a high-pressure gas into fermentation tank.

Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.

Abstract: A method of manufacturing double diffused drains in a semiconductor device. An embodiment comprises forming a gate dielectric layer on a substrate, and masking and patterning the gate dielectric layer. Once the gate dielectric layer has been patterned, a second dielectric layer, having a different depth than the gate dielectric layer, is deposited into the pattern. Once the dielectric layers have been placed into a step form, DDDs are formed by implanting ions through the two dielectric layers, whose different filtering properties form the DDDS. In another embodiment the implantations through the two dielectric layers are performed using different energies to form the different dose regions. In yet another embodiment the implantations are performed using different species (light and heavy), instead of different energies, to form the different dose regions.

Abstract: An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.