Patents by Inventor Hung-Ling Shih

Hung-Ling Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12277977
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Grant
    Filed: May 13, 2024
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Patent number: 12266577
    Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hung-Ling Shih, Tsung-Yu Yang, Yun-Chi Wu, Po-Wei Liu
  • Publication number: 20250038076
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a conductive structure disposed within a dielectric structure along a first side of a substrate. An insulating structure is disposed along inner sidewalls of the substrate and a blocking layer is disposed along a first inner sidewall and a second inner sidewall of the insulating structure, as viewed in a cross-sectional view. A through-substrate via (TSV) extends vertically through the substrate and along a horizontally-extending surface of the insulating structure. The horizontally-extending surface protrudes outward from the first inner sidewall of the insulating structure and towards the second inner sidewall of the insulating structure.
    Type: Application
    Filed: October 14, 2024
    Publication date: January 30, 2025
    Inventors: Hung-Ling Shih, Ming Chyi Liu, Jiech-Fun Lu
  • Patent number: 12211906
    Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen Tseng, Po-Wei Liu, Hung-Ling Shih, Tsung-Yu Yang, Tsung-Hua Yang, Yu-Chun Chang
  • Patent number: 12176266
    Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC). The IC includes a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate. An insulating structure is disposed along inner sidewalls of the semiconductor substrate. The inner sidewalls of the semiconductor substrate extend through the semiconductor substrate. A blocking layer is disposed along inner sidewalls of the insulating structure. A through-substrate via (TSV) includes a first portion and a second portion. The first portion extends from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure. The second portion extends from the first portion to the conductive structure and has a maximum width less than that of the first portion.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ling Shih, Ming Chyi Liu, Jiech-Fun Lu
  • Patent number: 12159803
    Abstract: In some embodiments, the present disclosure relates to a method that includes forming a shallow trench isolation (STI) structure that extends into a substrate. A masking layer is formed over the substrate and includes an opening overlying the STI structure. A first removal process removes portions of the STI structure underlying the opening of the STI structure. A second removal process laterally removes portions of the substrate below the STI structure. A third removal process removes portions of the substrate that directly underlie the opening of the masking layer. An insulator liner layer is formed within inner surfaces of the substrate as defined by the first, second, and third removal processes. Further, a fourth removal process removes portions of the insulator liner layer covering a lower surface of the substrate. A semiconductor material is then formed over the SOI substrate and on the insulator liner layer.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: December 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hung-Ling Shih
  • Publication number: 20240379716
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a stilted pad structure. A wire underlies a semiconductor substrate on a frontside of the semiconductor substrate. Further, a trench isolation structure extends into the frontside of the semiconductor substrate. The stilted pad structure is inset into a backside of the semiconductor substrate that is opposite the frontside. The stilted pad structure comprises a pad body and a pad protrusion. The pad protrusion underlies the pad body and protrudes from the pad body, through a portion of the semiconductor substrate and the trench isolation structure, towards the wire. The pad body overlies the portion of the semiconductor substrate and is separated from the trench isolation structure by the portion of the semiconductor substrate.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Sin-Yao Huang, Hung-Ling Shih, Kuo-Ming Wu, Hung-Wen Hsu
  • Publication number: 20240379771
    Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen TSENG, Po-Wei LIU, Hung-Ling SHIH, Tsung-Yu YANG, Tsung-Hua YANG, Yu-Chun CHANG
  • Publication number: 20240381637
    Abstract: A field effect transistor includes a source region and a drain region embedded in a portion of a semiconductor substrate; a gate dielectric overlying a channel region located between the source region and the drain region; a gate electrode overlying the gate dielectric; a dielectric gate liner laterally surrounding the gate electrode; a inner gate spacer laterally surrounding the dielectric gate liner; a contoured gate capping dielectric including a vertically-extending portion that laterally surrounds the inner gate spacer and a horizontally-extending portion that overlies the gate electrode; and a outer gate spacer laterally surrounding the contoured gate capping dielectric.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 14, 2024
    Inventors: Yu-Hsiang Yang, Chen-Ming Huang, Po-Wei Liu, Shih-Hsien Chen, Hung-Ling Shih, Chang Hung-Chang
  • Publication number: 20240373628
    Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Inventors: Wen-Tuo Huang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
  • Publication number: 20240355393
    Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Inventors: Shih Kuang Yang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin
  • Patent number: 12101931
    Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: September 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Tuo Huang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
  • Patent number: 12096629
    Abstract: Various embodiments of the present application are directed to a method for forming an integrated circuit (IC) comprising forming a multilayer film to form a plurality of memory cell structures disposed over a substrate and a plurality of memory test structures next to the memory cell structures. A memory test structure comprises a dummy control gate separated from the substrate by a dummy floating gate. The method further comprises forming a conductive floating gate test contact via along sidewalls of the dummy control gate and the dummy floating gate.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ling Shih, Yong-Shiuan Tsair
  • Publication number: 20240296890
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Patent number: 12068032
    Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Kuang Yang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin
  • Patent number: 12009033
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Publication number: 20240087988
    Abstract: The present disclosure, in some embodiments, relates an integrated chip. The integrated chip includes a substrate. A through-substrate-via (TSV) extends through the substrate. A dielectric liner separates the TSV from the substrate. The dielectric liner is along one or more sidewalls of the substrate. The TSV includes a horizontally extending surface and a protrusion extending outward from the horizontally extending surface. The TSV has a maximum width along the horizontally extending surface.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Hung-Ling Shih, Wei Chuang Wu, Shih Kuang Yang, Hsing-Chih Lin, Jen-Cheng Liu
  • Publication number: 20240088246
    Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Ling Hsu, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
  • Patent number: 11869951
    Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ling Hsu, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
  • Patent number: 11862535
    Abstract: The present disclosure relates an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate. The semiconductor substrate has one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate. A dielectric liner lines the one or more sidewalls of the semiconductor substrate. A through-substrate-via (TSV) is arranged between the one or more sidewalls and is separated from the semiconductor substrate by the dielectric liner. The TSV has a first width at a first distance from the second side and a second width at a second distance from the second side. The first width is smaller than the second width and the first distance is smaller than the second distance.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ling Shih, Wei Chuang Wu, Shih Kuang Yang, Hsing-Chih Lin, Jen-Cheng Liu