Patents by Inventor Hung-Ling Shih
Hung-Ling Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10541245Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.Type: GrantFiled: November 29, 2018Date of Patent: January 21, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: ShihKuang Yang, Yong-Shiuan Tsair, Po-Wei Liu, Hung-Ling Shih, Yu-Ling Hsu, Chieh-Fei Chiu, Wen-Tuo Huang
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Patent number: 10510544Abstract: A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.Type: GrantFiled: October 5, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Ling Hsu, Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Shihkuang Yang
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Publication number: 20190355731Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.Type: ApplicationFiled: May 16, 2018Publication date: November 21, 2019Inventors: Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair, Shih Kuang Yang
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Publication number: 20190229123Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.Type: ApplicationFiled: March 29, 2019Publication date: July 25, 2019Inventors: Tsun-Kai TSAO, Hung-Ling SHIH, Po-Wei LIU, Shun-Shing YANG, Wen-Tuo HUANG, Yong-Shiuan TSAIR, S.K. YANG
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Publication number: 20190157281Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.Type: ApplicationFiled: November 29, 2018Publication date: May 23, 2019Inventors: ShihKuang YANG, Yong-Shiuan TSAIR, Po-Wei LIU, Hung-Ling SHIH, Yu-Ling HSU, Chieh-Fei CHIU, Wen-Tuo HUANG
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Patent number: 10269818Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.Type: GrantFiled: March 7, 2018Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsun-Kai Tsao, Hung-Ling Shih, Po-Wei Liu, Shun-Shing Yang, Wen-Tuo Huang, Yong-Shiuan Tsair, S.K. Yang
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Patent number: 10269815Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.Type: GrantFiled: April 27, 2017Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: ShihKuang Yang, Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair
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Publication number: 20190067305Abstract: A method for forming a semiconductor structure includes providing a substrate including a plurality of first isolation structures formed therein, wherein the first isolation structures are protruded from a surface of the substrate; conformally forming a semiconductor layer over the substrate and the first isolation structures; forming a sacrificial layer over the semiconductor layer to form a planar surface over the substrate; and removing the sacrificial layer, a portion of the semiconductor layer and a portion of each first isolation structure to form at least one first gate structure using a same etchant.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Inventors: HUNG-LING SHIH, YONG-SHIUAN TSAIR, PO-WEI LIU, WEN-TUO HUANG, YU-LING HSU, CHIEH-FEI CHIU
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Patent number: 10204822Abstract: In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed conformal to the trench. A negatively-charged liner covering the lining oxide layer and conformal to the trench is formed. The trench is partially filled with a flowable oxide to a level below the top surface of the semiconductor substrate, and the flowable oxide in the trench is cured. The negatively-charged liner above the cured flowable oxide is optionally removed. A silicon oxide is deposited in the remaining portion of the trench, and a planarization process is performed to remove excess portions of the silicon oxide over the top surface of the semiconductor substrate.Type: GrantFiled: January 30, 2018Date of Patent: February 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hsien Chou, Hung-Ling Shih, Tsun-Kai Tsao, Ming-Huei Shen, Kuo-Hwa Tzeng, Yeur-Luen Tu
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Publication number: 20180315764Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90° <?1<115° measured from the upper surface of the erase gate.Type: ApplicationFiled: April 27, 2017Publication date: November 1, 2018Inventors: ShihKuang YANG, Hung-Ling SHIH, Chieh-Fei CHIU, Po-Wei LIU, Wen-Tuo HUANG, Yu-Ling HSU, Yong-Shiuan TSAIR
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Patent number: 10084056Abstract: A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap.Type: GrantFiled: March 20, 2017Date of Patent: September 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Wen Hsu, Hung-Ling Shih, Jiech-Fun Lu
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Publication number: 20180269299Abstract: A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap.Type: ApplicationFiled: March 20, 2017Publication date: September 20, 2018Inventors: Hung-Wen Hsu, Hung-Ling Shih, Jiech-Fun Lu
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Publication number: 20180197873Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.Type: ApplicationFiled: March 7, 2018Publication date: July 12, 2018Inventors: Tsun-Kai TSAO, Hung-Ling SHIH, Po-Wei LIU, Shun-Shing YANG, Wen-Tuo HUANG, Yong-Shiuan TSAIR, S.K. Yang
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Publication number: 20180174888Abstract: In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed conformal to the trench. A negatively-charged liner covering the lining oxide layer and conformal to the trench is formed. The trench is partially filled with a flowable oxide to a level below the top surface of the semiconductor substrate, and the flowable oxide in the trench is cured. The negatively-charged liner above the cured flowable oxide is optionally removed. A silicon oxide is deposited in the remaining portion of the trench, and a planarization process is performed to remove excess portions of the silicon oxide over the top surface of the semiconductor substrate.Type: ApplicationFiled: January 30, 2018Publication date: June 21, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hsien CHOU, Hung-Ling SHIH, Tsun-Kai TSAO, Ming-Huei SHEN, Kuo-Hwa TZENG, Yeur-Luen TU
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Patent number: 9997524Abstract: A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.Type: GrantFiled: September 21, 2016Date of Patent: June 12, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Tsun-Kai Tsao, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair
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Publication number: 20180151375Abstract: A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and. the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.Type: ApplicationFiled: October 5, 2017Publication date: May 31, 2018Inventors: Yu-Ling HSU, Hung-Ling SHIH, Chieh-Fei CHIU, Po-Wei LIU, Wen-Tuo HUANG, Yong-Shiuan TSAIR, Shihkuang YANG
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Patent number: 9929167Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.Type: GrantFiled: July 13, 2016Date of Patent: March 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsun-Kai Tsao, Hung-Ling Shih, Po-Wei Liu, Shun-Shing Yang, Wen-Tuo Huang, Yong-Shiuan Tsair, S. K. Yang
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Patent number: 9917003Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.Type: GrantFiled: June 28, 2013Date of Patent: March 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hsien Chou, Hung-Ling Shih, Tsun-Kai Tsao, Ming-Huei Shen, Kuo-Hwa Tzeng, Yeur-Luen Tu
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Publication number: 20180061847Abstract: A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.Type: ApplicationFiled: September 21, 2016Publication date: March 1, 2018Inventors: Hung-Ling SHIH, Chieh-Fei CHIU, Po-Wei LIU, Tsun-Kai TSAO, Wen-Tuo HUANG, Yu-Ling HSU, Yong-Shiuan TSAIR
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Publication number: 20180019251Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.Type: ApplicationFiled: July 13, 2016Publication date: January 18, 2018Inventors: Tsun-Kai TSAO, Hung-Ling SHIH, Po-Wei LIU, Shun-Shing YANG, Wen-Tuo HUANG, Yong-Shiuan TSAIR, S.K. Yang