Patents by Inventor Hung-Ming Chen
Hung-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240331592Abstract: A display apparatus and an image processing method thereof are provided. The display apparatus includes a display panel and an image processing device. The image processing device receives a low-resolution image from a host. The image processing device tracks a user's gaze to define a region of interest (ROI). The image processing device performs a video super-resolution (VSR) reconstruction on an original ROI image corresponding to the ROI in the low-resolution image to generate a high-definition ROI image. The image processing device pastes the high-definition ROI image back to the ROI in the low-resolution image to generate a processed image. The image processing device controls the display panel to display the processed image.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Novatek Microelectronics Corp.Inventors: Hung-Ming Wang, Sin-Hong Li, Yi-Ting Chen, Chih-Hung Kuo, Ting-Chou Tsai
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Publication number: 20240332076Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.Type: ApplicationFiled: June 10, 2024Publication date: October 3, 2024Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
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Patent number: 12100898Abstract: An antenna module includes a feeding end, multiple first forked radiators, and multiple connecting parts. The first forked radiators are disposed side by side. The connecting parts respectively extend from the feeding end to the first forked radiators. The feeding end, the first forked radiators, and the connecting parts are located on a same plane. The antenna module resonates at a frequency band, and a path length from the feeding end to an end of each of the forked radiators through the corresponding connecting part is ΒΌ wavelength of the frequency band.Type: GrantFiled: September 8, 2022Date of Patent: September 24, 2024Assignee: PEGATRON CORPORATIONInventors: Chien-Yi Wu, Wu-Hua Chen, I-Shu Lee, Hung-Ming Yu, Chao-Hsu Wu, Yung-Yi Lee, Man-Jung Tsao, Chi-Min Tang, Shao-Chi Wang
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Publication number: 20240304584Abstract: A package structure is provided. The package structure includes a semiconductor substrate. The semiconductor substrate includes a lower portion and an upper portion. The upper portion of the semiconductor substrate defines a high speed signal transmission region. The high speed signal transmission region includes a first region configured to communicate with a first electronic component and a second region configured to communicate with an external device.Type: ApplicationFiled: March 8, 2023Publication date: September 12, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hai-Ming CHEN, Hung-Yi LIN, Cheng-Yuan KUNG
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Publication number: 20240305462Abstract: The present invention relates to an authentication information manager computer program product, which is executed by a processing unit. The computer program product includes: a physical private key acquisition module configured to receive an identity information to form an initialization authentication information including a part of the identity information; an authentication information management module configured to record a first set of authentication information for logging into a first networking application; and a multiparty multifactor dynamic strong encryption authentication transmission module configured to implement a multiparty multifactor dynamic digital authentication method with strong encryption to transmit the transfigurated initialization authentication information to a network application serving device including an authentication information manager back end and a third-party security serving equipment to be verified.Type: ApplicationFiled: September 25, 2023Publication date: September 12, 2024Inventors: Tsu-Pin WENG, Wu-Hsiung HUANG, Jia-You JIANG, Yi-Yuan HO, Hung-Ming CHEN, Yuan-Sheng CHEN
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Patent number: 12087642Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.Type: GrantFiled: April 28, 2023Date of Patent: September 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yip Loh, Yan-Ming Tsai, Yi-Ning Tai, Raghunath Putikam, Hung-Yi Huang, Hung-Hsu Chen, Chih-Wei Chang
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Patent number: 12087767Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.Type: GrantFiled: December 20, 2022Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hung-Chin Chung, Hsien-Ming Lee, Chi On Chui, Hsuan-Yu Tung, Chung-Chiang Wu
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Patent number: 12082235Abstract: A system and a method of random access resource selection are provided. The method includes a target Base Station (BS) transmitting a first Synchronization Signal Block (SSB) to a User Equipment (UE), the first SSB associated with a first contention-free random access resource for the UE to transmit a random access preamble; the target BS transmitting a second SSB to the UE, the second SSB associated with a contention-based random access resource; and in a case that a first Synchronization Signal-Reference Signal Received Power (SS-RSRP) of the first SSB is not greater than an SS-RSRP threshold and a second SS-RSRP of the second SSB is greater than the SS-RSRP threshold, the target BS receiving the random access preamble from the UE using the contention-based random access resource.Type: GrantFiled: May 23, 2023Date of Patent: September 3, 2024Assignee: FG Innovation Company LimitedInventors: Hung-Chen Chen, Chie-Ming Chou, Yu-Hsin Cheng, Mei-Ju Shih
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Publication number: 20240290629Abstract: A method for CMP includes following operations. A first metal layer and a second metal layer are formed in a dielectric structure. The second metal layer is formed over a portion of the first metal layer. A first composition is provided to remove a portion of the first metal layer. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed to expose the second metal layer. A CMP operation is performed to remove a portion of the first metal layer, a portion of the second metal layer and a portion of the dielectric structure.Type: ApplicationFiled: April 29, 2024Publication date: August 29, 2024Inventors: JI CUI, FU-MING HUANG, TING-KUI CHANG, TANG-KUEI CHANG, CHUN-CHIEH LIN, WEI-WEI LIANG, LIANG-GUANG CHEN, KEI-WEI CHEN, HUNG YEN, TING-HSUN CHANG, CHI-HSIANG SHEN, LI-CHIEH WU, CHI-JEN LIU
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Publication number: 20240277224Abstract: The invention provides an optical coherence tomography self-testing system, an optical coherence tomography method and an ocular disease monitoring system. The optical coherence tomography self-testing system comprises a camera device, an external display module and a communication module. The camera device includes an image-capturing module and a processing module. The image-capturing module captures a plurality of ocular images. The processing module is connected to the image-capturing module, and the processing module determines whether a position offset value between the pupil center position of a tested eyeball and an optical axis of the image-capturing module is within a preset error range. If the position offset value is within the preset error range, the plurality of ocular images is stored as a plurality of displayed images. The external display module displays one of the plurality of displayed images and a status light after the image-capturing module has completed image capturing.Type: ApplicationFiled: December 14, 2023Publication date: August 22, 2024Inventors: Chu-Ming Cheng, Wei Ting Tseng, LI-REN CAI, Hung-Chin Chen, CHIEN-CHI HUANG, Yung-En Kuo, PEI-SHENG WU
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Publication number: 20240277865Abstract: Disclosed herein is a phage-displayed single-chain variable fragment (scFv) library, which comprises a plurality of phage-displayed scFvs characterized with a specific sequence in each CDR. The present phage-displayed scFv library is useful in selecting an antibody fragment exhibiting a binding affinity and specificity to mesothelin (MSLN). Also disclosed herein are a recombinant antibody specific to MSLN, an immunoconjugate comprising the recombinant antibody, and uses thereof in treating cancers.Type: ApplicationFiled: June 8, 2022Publication date: August 22, 2024Inventors: An-Suei YANG, Hung-Ju HSU, Chao-Ping TUNG, Chung-Ming YU, Chi-Yung CHEN, Hong-Sen CHEN, Yu-Chuan HUANG, Pei-Hsun TSAI, Szu-Yu LIN, Hung-Pin PENG
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Patent number: 12067164Abstract: Techniques for proving haptic feedback in computing systems are described. In operation, an input representing utilisation parameters of an electronic pen is received. In an example, the electronic pen may be electronically coupled to the computing system. Based on the received utilisation parameters, the computing system provides a pattern of haptic feedback to the user.Type: GrantFiled: September 16, 2019Date of Patent: August 20, 2024Assignee: Hewlett-Packard Development Company, L.P.Inventors: Charles J. Stancil, Tai Hsiang Chen, Hung-Ming Chen, Simon Wong, Hsiang-Ta Ke, Yi-Hsien Lin, Jung-Hsing Wang
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Patent number: 12068271Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.Type: GrantFiled: July 23, 2023Date of Patent: August 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Chi Chen, Hsun-Ying Huang, Chih-Ming Lee, Shang-Yen Wu, Chih-An Yang, Hung-Wei Ho, Chao-Ching Chang, Tsung-Wei Huang
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Patent number: 12062687Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.Type: GrantFiled: June 28, 2023Date of Patent: August 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hong-Yang Chen, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen, Kuo-Ming Wu, Chiu-Hua Chung
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Publication number: 20240266232Abstract: A high atomic number material is applied to one or more surfaces of a semiconductor structure of a wafer. The one or more surfaces are at a depth different from a depth of a surface of the wafer. An electron beam is scanned over the semiconductor structure to cause a backscattered electron signal to be collected at a collector. A profile scan of the semiconductor structure is generated based on an intensity of the backscattered electron signal, at the collector, resulting from the high atomic number material. The high atomic number material increases the intensity of the backscattered electron signal for the one or more surfaces of the semiconductor structure such that contrast in the profile scan is increased. The increased contrast of the profile scan enables accurate critical dimension measurements of the semiconductor structure.Type: ApplicationFiled: April 3, 2024Publication date: August 8, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Hsuan LEE, Hung-Ming CHEN, Kuang-Shing CHEN, Yu-Hsiang CHENG, Xiaomeng CHEN
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Patent number: 12058604Abstract: A method for a system information (SI) request procedure performed by a user equipment (UE) is provided. The method includes: receiving a system information block type 1 (SIB1) from a cell; transmitting, to the cell, a first message including a common control channel (CCCH) service data unit (SDU) that includes a radio resource control (RRC) SI request message; receiving, from the cell, a medium access control (MAC) control element (CE) including a UE contention resolution identity; and indicating, by a MAC entity of the UE, reception of an acknowledgment for the RRC SI request message to an RRC entity of the UE after determining that the UE contention resolution identity matches multiple consecutive bits, starting from the most significant bit (MSB), of the CCCH SDU. The SIB1 does not include information related to a Random Access (RA) resource specific to SI requested by the RRC SI request message.Type: GrantFiled: May 31, 2023Date of Patent: August 6, 2024Assignee: FG Innovation Company LimitedInventors: Mei-Ju Shih, Chie-Ming Chou, Hung-Chen Chen, Yung-Lan Tseng
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Patent number: 12058625Abstract: A method by a base station for receiving power headroom reporting from a user equipment (UE) in a Multi-Radio Access Technology (RAT)-Dual Connectivity (MR-DC) scenario, the method includes receiving a DC Power Headroom Report (PHR) Medium Access Control (MAC) Control Element (CE) from the UE, the DC PHR MAC CE having a fixed number of octets with cell index fields for indicating whether a power headroom (PH) for a serving cell with a corresponding cell index is reported, wherein the fixed number of octets is independent of a highest secondary Cell Index (SCellIndex) for serving cells with configured uplinks.Type: GrantFiled: November 15, 2021Date of Patent: August 6, 2024Inventors: Hung-Chen Chen, Chie-Ming Chou
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Patent number: 12046510Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.Type: GrantFiled: June 4, 2021Date of Patent: July 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
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Patent number: 12040235Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: GrantFiled: July 21, 2022Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
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Patent number: 11984365Abstract: A high atomic number material is applied to one or more surfaces of a semiconductor structure of a wafer. The one or more surfaces are at a depth different from a depth of a surface of the wafer. An electron beam is scanned over the semiconductor structure to cause a backscattered electron signal to be collected at a collector. A profile scan of the semiconductor structure is generated based on an intensity of the backscattered electron signal, at the collector, resulting from the high atomic number material. The high atomic number material increases the intensity of the backscattered electron signal for the one or more surfaces of the semiconductor structure such that contrast in the profile scan is increased. The increased contrast of the profile scan enables accurate critical dimension measurements of the semiconductor structure.Type: GrantFiled: March 19, 2021Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Hsuan Lee, Hung-Ming Chen, Kuang-Shing Chen, Yu-Hsiang Cheng, Xiaomeng Chen