Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: An automatic robotic arm system and a coordinating method for robotic arm and computer vision thereof are disclosed. A beam-splitting mirror splits an incident light into a visible light and a ranging light and respectively guides to an image capturing device and an optical ranging device arranged in the different reference axes. In a calibration mode, a transformation relation is computed based on a plurality of the calibration postures and corresponding calibration images. In an operation mode, a mechanical space coordinate is determined based on an operation image and the transformation relation, and the robotic arm is controlled to move based on the mechanical space coordinate.

Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.

Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.

Abstract: A compound of Formula (I) below, or a pharmaceutically acceptable salt, stereoisomer, solvate, or prodrug thereof: in which R1, R2, R3, R5, R6, and R7 are defined as in the SUMMARY section. Further disclosed are a method of using the above-described compound, salt, stereoisomer, solvate, or prodrug for treating microbial infections and a pharmaceutical composition containing the same.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: A user equipment (UE) and a method performed by the UE are provided. The method includes transitioning from a radio resource control (RRC) inactive (RRC_INACTIVE) state to an RRC idle (RRC_IDLE) state upon determining that the UE has failed to find a suitable cell and camped on an acceptable cell; and discarding a radio access network (RAN) notification area (RNA) configuration that comprises at least one of a list of tracking area identities (IDs) or a list of RAN area IDs in response to the transitioning from the RRC_INACTIVE state to the RRC_IDLE state. The acceptable cell fulfills a minimum set of requirements to initiate an emergency call and to receive one or more Earthquake & Tsunami Warning System (ETWS) and Commercial Mobile Alert System (CMAS) notifications. The suitable cell provides normal services. The acceptable cell provides limited services.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A method for LBT failure detection performed by a UE is provided. The method includes: receiving, by a MAC entity of the UE, an LBT failure indication from a lower layer for all UL transmissions; increasing an LBT failure counter when the MAC entity receives the LBT failure indication; determining an LBT failure event occurs when the LBT failure counter is greater than or equal to a threshold; and resetting the LBT failure counter after the MAC entity has not received the LBT failure indication for a time period.

Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

Abstract: A gaming system and an operation method of a gaming server thereof are provided. The gaming system includes multiple player devices and the gaming server. The gaming server establishes a network connection with the player devices. In response to one of the player devices initiating a game, the gaming server sends a game notification to the player devices according to a player list. The gaming server determines a common throughput between the player devices based on a response of each of the player devices to the game notification.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.

Abstract: A method performed by a BS for CHO is provided. The method includes transmitting a CHO command to a UE, the CHO command including a CHO command ID and a measurement ID associated with the CHO command ID; causing the UE to execute the CHO command to handover to a target BS when a trigger condition associated with the measurement ID is fulfilled; causing the UE to forgo transmitting the measurement report during the execution of the CHO command despite the UE being configured, via a report configuration associated with the measurement ID, to transmit the measurement report; transmitting, to the UE, a message that causes the UE to remove the CHO command; and after transmitting the message to the UE, determining that the report configuration is removed by the UE without transmitting, to the UE, an instruction to remove the report configuration.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: In some examples, an electronic device includes an image sensor to capture a source image. In some examples, the electronic device includes a processor to determine, in the source image, a first region that depicts a first person and a second region that depicts a second person. In some examples, the processor is to, in response to determining that the first person is further away than the second person relative to the image sensor based on the first region and the second region, generate a first focus cell that depicts the first person alone. In some examples, the processor is to generate a macro view of the source image that depicts the first person and the second person. In some examples, the processor is to instruct display of a compound image including the macro view and the first focus cell.

Abstract: In some examples, an electronic device includes an image sensor to capture a source image. In some examples, the electronic device includes a processor to determine, in the source image, a first region that depicts a first person and a second region that depicts a second person. In some examples, the processor is to, in response to determining that the first person is further away than the second person relative to the image sensor based on the first region and the second region, generate a first focus cell that depicts the first person alone. In some examples, the processor is to generate a macro view of the source image that depicts the first person and the second person. In some examples, the processor is to instruct display of a compound image including the macro view and the first focus cell.

Abstract: An example non-transitory machine-readable storage medium includes instructions to, when executed by the processor, identify an object depicted in a video scene, wherein the video scene is displayed in a graphical user interface (GUI). The example instructions are executable to 1) identify coordinates of the object depicted in the video scene, wherein the coordinates are relative to the GUI and 2) identify coordinates of an inset window which is smaller than the GUI and overlaps the video scene. The example instructions are executable to compare the coordinates of the object with the coordinates of the inset window to determine an overlap of the inset window with the object. Responsive to an identified overlap of the inset window and the object, the instructions are executable to alter a display characteristic of the inset window to avoid the overlap of the inset window with the object.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.