Patents by Inventor Hung-Ming Tsai

Hung-Ming Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953740
    Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11955443
    Abstract: A manufacturing method of a flip chip package structure is provided and has following steps: providing at least one silicon substrate having a connecting surface and at least one conductive base attached to the connecting surface; arranging a graphene copper layer covering the conductive base; laminating a photoresist layer on the connecting surface, etching the photoresist layer to form a cavity corresponding to the conductive base, and a portion of the graphene copper layer corresponding to the conductive base being exposed on a bottom of the cavity; electroplating a copper material on the graphene copper layer, and the copper material being accumulated in the cavity to form a copper pillar; removing the photoresist layer and the graphene copper layer covered by the photoresist layer.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: April 9, 2024
    Assignee: AMAZING COOL TECHNOLOGY CORP.
    Inventors: Shiann-Tsong Tsai, Yang-Ming Shih, Hung-Yun Hsu
  • Patent number: 11947173
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11946569
    Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Shih-Chang Chen, Jia-Yu Liao, Hung-Hsin Liao, Chung-Wei Kao, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee
  • Patent number: 11942543
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Patent number: 9825628
    Abstract: An electronic device includes a transmission interface and a control circuit. The transmission interface includes a signal reference contact and a signal transmission contact. The control circuit is electrically coupled between the signal reference contact and a ground layer, in which the control circuit is configured to selectively conduct the signal reference contact and the ground layer, and when the signal reference contact and the ground layer are conducted, the signal transmission contact is configured to transmit a first signal, and when the signal reference contact the ground layer are not conducted, the signal reference contact is configured to transmit a second signal. A transmission frequency of the second signal is less than a transmission frequency of the first signal.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: November 21, 2017
    Assignee: Synology Incorporated
    Inventors: Yen-Li Hsieh, Ming-Hung Tsai, Hung-Ming Tsai
  • Patent number: 9766749
    Abstract: A touch device and a sensing compensation method are provided. The touch device may include a touch panel, a sensing compensation circuit and a sensing circuit. The sensing compensation circuit may be coupled to the touch panel for providing a compensation-impedance according to features of the touch panel. The sensing circuit may be coupled to the sensing compensation circuit. The sensing circuit receives touch information compensated by the sensing compensation circuit.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: September 19, 2017
    Assignee: Industrial Technology Research Institute
    Inventors: Yen-Lin Pan, Wei-Yen Lee, Chang-Po Chao, Hung-Ming Tsai, Hsuan-Wen Peng
  • Publication number: 20170026038
    Abstract: An electronic device includes a transmission interface and a control circuit. The transmission interface includes a signal reference contact and a signal transmission contact. The control circuit is electrically coupled between the signal reference contact and a ground layer, in which the control circuit is configured to selectively conduct the signal reference contact and the ground layer, and when the signal reference contact and the ground layer are conducted, the signal transmission contact is configured to transmit a first signal, and when the signal reference contact the ground layer are not conducted, the signal reference contact is configured to transmit a second signal. A transmission frequency of the second signal is less than a transmission frequency of the first signal.
    Type: Application
    Filed: October 3, 2016
    Publication date: January 26, 2017
    Inventors: Yen-Li HSIEH, Ming-Hung TSAI, Hung-Ming TSAI
  • Patent number: 9490799
    Abstract: An electronic device includes a transmission interface, a switch unit and a control unit. The transmission interface includes a signal reference contact and a signal transmission contact. The switch unit is coupled between the signal reference contact and a grounded layer. The control unit is coupled to the switch unit. When the control unit controls the switch unit to connect the signal reference contact and the grounded layer, the signal transmission contact is used to transmit a first signal. When the control unit controls the switch unit to disconnect the signal reference contact from the grounded layer, the signal reference contact is used to transmit a second signal.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: November 8, 2016
    Assignee: Synology Incorporated
    Inventors: Yen-Li Hsieh, Ming-Hung Tsai, Hung-Ming Tsai
  • Publication number: 20150340320
    Abstract: A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed.
    Type: Application
    Filed: August 4, 2015
    Publication date: November 26, 2015
    Inventors: Sanjeev Sapra, Cheng-Shun Chen, Hung-Ming Tsai, Sheng-Wei Yang
  • Publication number: 20150303147
    Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.
    Type: Application
    Filed: June 26, 2015
    Publication date: October 22, 2015
    Inventors: Jaydeb Goswami, Hung Ming Tsai, Duane M. Goodner
  • Patent number: 9147604
    Abstract: A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: September 29, 2015
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Vivek Gopalan, Robert Kerr, Hung-Ming Tsai
  • Patent number: 9123784
    Abstract: A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: September 1, 2015
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Vivek Gopalan, Robert Kerr, Hung-Ming Tsai
  • Patent number: 9117759
    Abstract: A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: August 25, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Sanjeev Sapra, Cheng-Shun Chen, Hung-Ming Tsai, Sheng-Wei Yang
  • Patent number: 9099472
    Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jaydeb Goswami, Hung Ming Tsai, Duane M. Goodner
  • Publication number: 20150214944
    Abstract: An electronic device includes a transmission interface, a switch unit and a control unit. The transmission interface includes a signal reference contact and a signal transmission contact. The switch unit is coupled between the signal reference contact and a grounded layer. The control unit is coupled to the switch unit. When the control unit controls the switch unit to connect the signal reference contact and the grounded layer, the signal transmission contact is used to transmit a first signal. When the control unit controls the switch unit to disconnect the signal reference contact from the grounded layer, the signal reference contact is used to transmit a second signal.
    Type: Application
    Filed: June 11, 2014
    Publication date: July 30, 2015
    Inventors: Yen-Li HSIEH, Ming-Hung TSAI, Hung-Ming TSAI
  • Patent number: 9054216
    Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 9, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
  • Publication number: 20150111377
    Abstract: A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
    Type: Application
    Filed: December 24, 2014
    Publication date: April 23, 2015
    Inventors: Vivek Gopalan, Robert Kerr, Hung-Ming Tsai
  • Patent number: 8921183
    Abstract: A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: December 30, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Jen-Jui Huang, Hung-Ming Tsai
  • Publication number: 20140375600
    Abstract: A touch device and a sensing compensation method are provided. The touch device may include a touch panel, a sensing compensation circuit and a sensing circuit. The sensing compensation circuit may be coupled to the touch panel for providing a compensation-impedance according to features of the touch panel. The sensing circuit may be coupled to the sensing compensation circuit. The sensing circuit receives touch information compensated by the sensing compensation circuit.
    Type: Application
    Filed: January 24, 2014
    Publication date: December 25, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Yen-Lin Pan, Wei-Yen Lee, Chang-Po Chao, Hung-Ming Tsai, Hsuan-Wen Peng