Abstract: The image processing IC includes a down-scaler circuit, a picture quality processing circuit, and an up-scaler circuit. The down-scaler circuit converts a first image frame with a first resolution into a second image frame with a second resolution smaller than the first resolution by using a down-scaling operation. The picture quality processing circuit performs at least one picture quality processing on the second image frame to generate a third image frame. The up-scaler circuit converts the third image frame with a third resolution into a fourth image frame with a fourth resolution greater than the third resolution by using an up-scaling operation. The up-scaling operation performed by the up-scaler circuit is symmetrical to the down-scaling operation performed by the down-scaler circuit.

Abstract: The invention provides an image processing method and an image processing device. The image processing method comprises: performing a first weighted average calculation on a plurality of luminance data of pixels in a first mask, to obtain a background average value with respect to a target pixel which is a center pixel of the first mask; performing a second weighted average calculation on a plurality of luminance data of pixels in a second mask, to obtain a foreground average value with respect to the target pixel which is also a center pixel of the second mask; generating a sharpness level according to a gain value and a difference between luminance data of the target pixel and the foreground average value with respect to the target pixel; and, adjusting the luminance data of the target pixel according to the sharpness level.

Abstract: In accordance with embodiments of the present disclosure, an anode is presented. The anode includes a first anode material, the first anode material having a flat side and an embossed side that is embossed with a first embossing pattern; and a second anode material, the second anode material having a flat side and an embossed side that is embossed with a second embossing pattern, wherein the embossed side of the first anode material is positioned against the embossed side of the second anode material, and wherein the first anode material and the second anode material are coupled on one edge.

Abstract: A display apparatus and an image processing method thereof are provided. The display apparatus includes a display panel and an image processing device. The image processing device receives a low-resolution image from a host. The image processing device tracks a user's gaze to define a region of interest (ROI). The image processing device performs a video super-resolution (VSR) reconstruction on an original ROI image corresponding to the ROI in the low-resolution image to generate a high-definition ROI image. The image processing device pastes the high-definition ROI image back to the ROI in the low-resolution image to generate a processed image. The image processing device controls the display panel to display the processed image.

Abstract: An operation method performed by an image processor is provided, including the following operations of receiving a mixed image including an input image and a first on-screen-display (OSD) pattern and generating a second OSD pattern, different from the first OSD pattern, based on the mixed image. The second OSD pattern encompasses protection regions of the input image, and the protection regions are in close proximity of the first OSD pattern. The method further includes operations of performing image processing to remaining regions, different from the protection regions, of the input image and generating an output image. The output image includes the second OSD pattern and the remaining regions of the input image, being performed by the image processing.

Abstract: The image processing IC includes a down-scaler circuit, a picture quality processing circuit, and an up-scaler circuit. The down-scaler circuit converts a first image frame with a first resolution into a second image frame with a second resolution smaller than the first resolution by using a down-scaling operation. The picture quality processing circuit performs at least one picture quality processing on the second image frame to generate a third image frame. The up-scaler circuit converts the third image frame with a third resolution into a fourth image frame with a fourth resolution greater than the third resolution by using an up-scaling operation. The up-scaling operation performed by the up-scaler circuit is symmetrical to the down-scaling operation performed by the down-scaler circuit.

Abstract: An operation method performed by an image processor is provided, including the following operations: receiving a mixed image including an input image and a first on-screen-display (OSD) pattern; generating a second OSD pattern, different from the first OSD pattern, based on the mixed image. The second OSD pattern encompasses protection regions of the input image, and the protection regions are in close proximity of the first OSD pattern. The method further includes operations of performing image processing to remaining regions, different from the protection regions, of the input image and generating an output image. The output image includes the second OSD pattern and the remaining regions of the input image, being performed by the image processing.

Abstract: A display apparatus and an image processing method thereof are provided. The display apparatus includes a display panel and an image processing device. The image processing device receives a low-resolution image from a host. The image processing device tracks a user's gaze to define a region of interest (ROI). The image processing device performs a video super-resolution (VSR) reconstruction on an original ROI image corresponding to the ROI in the low-resolution image to generate a high-definition ROI image. The image processing device pastes the high-definition ROI image back to the ROI in the low-resolution image to generate a processed image. The image processing device controls the display panel to display the processed image.

Abstract: A wafer plating fixture for use in simultaneously electroplating a two substrates. The wafer plating fixture including: an electrically conductive carrier bus; a plurality of contact clips electrically coupled to the carrier bus and configured to hold the two substrates in place and electrically couple the two substrates to the carrier bus; and a non-conductive substrate backer to separate the two substrates coupled to the carrier bus. A method of electroplating a plurality of substrates. The method including: mounting two substrates to be plated onto a wafer plating fixture; mounting the wafer plating fixture on a continuous belt of plating system; dipping the wafer plating fixture with the two substrates held thereon into an electroplating bath; and applying a voltage to the two substrates via the wafer plating fixture.

Abstract: A device and method for blending image data and the alpha channel and reconstructing to obtain the image again after transmission. An encoder blends the alpha channel and the red-green-blue (RGB) image data through a layer blending method that is supported by the general application processor (AP). Transporter image data, such as a checkerboard pattern, is blended with 1-alpha channel data to obtain a transporter. The blended image data (RGB+alpha) is mixed with the transporter to obtain mixed image data. The mixed image data is then transmitted through the existing transmission interface. After receiving the mixed image data, reconstruction processing is performed by a decoder to obtain the original RGB image data and the alpha channel again.

Abstract: Methods of fabricating solar cells having a plurality of sub-cells coupled by cell level interconnection, and the resulting solar cells, are described herein. In an example, a solar cell includes a plurality of sub-cells. Each of the plurality of sub-cells includes a singulated and physically separated semiconductor substrate portion. Each of the plurality of sub-cells includes an on-sub-cell metallization structure interconnecting emitter regions of the sub-cell. An inter-sub-cell metallization structure couples adjacent ones of the plurality of sub-cells. The inter-sub-cell metallization structure is different in composition from the on-sub-cell metallization structure.

Abstract: A wafer plating fixture for use in simultaneously electroplating a two substrates. The wafer plating fixture including: an electrically conductive carrier bus; a plurality of contact clips electrically coupled to the carrier bus and configured to hold the two substrates in place and electrically couple the two substrates to the carrier bus; and a non-conductive substrate backer to separate the two substrates coupled to the carrier bus. A method of electroplating a plurality of substrates. The method including: mounting two substrates to be plated onto a wafer plating fixture; mounting the wafer plating fixture on a continuous belt of plating system; dipping the wafer plating fixture with the two substrates held thereon into an electroplating bath; and applying a voltage to the two substrates via the wafer plating fixture.

Abstract: A method for generating a plurality of on-screen display (OSD) data is used in a back-end (BE) circuit. The BE circuit is configured to process a plurality of image data to be displayed on a display device. The method includes steps of: receiving the plurality of image data from an application processor (AP); and extracting information of a detecting layer embedded in the plurality of image data, wherein the information of the detecting layer indicates the plurality of OSD data corresponding to at least one user-interface (UI) layer in the plurality of image data.

Abstract: A wafer plating fixture for use in simultaneously electroplating a two substrates. The wafer plating fixture including: an electrically conductive carrier bus; a plurality of contact clips electrically coupled to the carrier bus and configured to hold the two substrates in place and electrically couple the two substrates to the carrier bus; and a non-conductive substrate backer to separate the two substrates coupled to the carrier bus. A method of electroplating a plurality of substrates. The method including: mounting two substrates to be plated onto a wafer plating fixture; mounting the wafer plating fixture on a continuous belt of plating system; dipping the wafer plating fixture with the two substrates held thereon into an electroplating bath; and applying a voltage to the two substrates via the wafer plating fixture.

Abstract: Methods of fabricating solar cells having a plurality of sub-cells coupled by cell level interconnection, and the resulting solar cells, are described herein. In an example, a solar cell includes a plurality of sub-cells. Each of the plurality of sub-cells includes a singulated and physically separated semiconductor substrate portion. Each of the plurality of sub-cells includes an on-sub-cell metallization structure interconnecting emitter regions of the sub-cell. An inter-sub-cell metallization structure couples adjacent ones of the plurality of sub-cells. The inter-sub-cell metallization structure is different in composition from the on-sub-cell metallization structure.

Abstract: The present invention provides a method for generating a plurality of on-screen display (OSD) data used in a back-end (BE) circuit. The BE circuit is configured to process a plurality of image data to be displayed on a display device. The method includes steps of: receiving the plurality of image data from an application processor (AP); and extracting information of a detecting layer embedded in the plurality of image data, wherein the information of the detecting layer indicates the plurality of OSD data corresponding to at least one user-interface (UI) layer in the plurality of image data.

Abstract: Methods of fabricating solar cells having a plurality of sub-cells coupled by cell level interconnection, and the resulting solar cells, are described herein. In an example, a solar cell includes a plurality of sub-cells. Each of the plurality of sub-cells includes a singulated and physically separated semiconductor substrate portion. Each of the plurality of sub-cells includes an on-sub-cell metallization structure interconnecting emitter regions of the sub-cell. An inter-sub-cell metallization structure couples adjacent ones of the plurality of sub-cells. The inter-sub-cell metallization structure is different in composition from the on-sub-cell metallization structure.

Abstract: A device and method for blending image data and the alpha channel and reconstructing to obtain the image again after transmission. An encoder blends the alpha channel and the red-green-blue (RGB) image data through a layer blending method that is supported by the general application processor (AP). Transporter image data, such as a checkerboard pattern, is blended with 1-alpha channel data to obtain a transporter. The blended image data (RGB+alpha) is mixed with the transporter to obtain mixed image data. The mixed image data is then transmitted through the existing transmission interface. After receiving the mixed image data, reconstruction processing is performed by a decoder to obtain the original RGB image data and the alpha channel again.

Abstract: A solar cell and a solar laminate are described. The solar cell can have a front side which faces the sun during normal operation and a back side opposite front side. The solar cell can include conductive contacts having substantially reflective outer regions disposed on the back side of the solar cell. The solar laminate can include a first encapsulant, the first encapsulant disposed on the back side of the solar cell and a second encapsulant. The solar laminate can include the solar cell laminated between the first and second encapsulant. The substantially reflective outer regions of the conductive contacts and the first encapsulant can be configured to scatter and/or diffuse light at the back side of the solar laminate for substantial light collection at the back side of the solar cell. Methods of fabricating the solar cell are also described herein.

Abstract: Solar cells are attached together to form a plating assembly. The plating assembly is attached to a belt, which transports the plating assembly through a plating chamber where metal is electroplated on the solar cells. The electroplated metal is patterned to form metal contact fingers. After the metal is electroplated, the plating assembly is singulated to separate the two solar cells.